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43 条记录 (耗时 0.027 秒)

    Method to preserve alignment mark optical integrity
    11.
    发明授权
    Method to preserve alignment mark optical integrity 有权
    保持对准标记光学完整性的方法

    公开(公告)号：US06803291B1

    公开(公告)日：2004-10-12

    申请号：US10394089

    申请日：2003-03-20

    申请人： Shih-Chi Fu ,  Feng-Jia Shih ,  Chia-Tung Ho ,  Chih-Ta Wu ,  Ching-Sen Kuo ,  Jieh-Jang Chen ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsia

    发明人： Shih-Chi Fu ,  Feng-Jia Shih ,  Chia-Tung Ho ,  Chih-Ta Wu ,  Ching-Sen Kuo ,  Jieh-Jang Chen ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsia

    IPC分类号： H01L2176

    CPC分类号： H01L21/76229 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for protecting an alignment mark area during a CMP process including forming at least a first material layer over a process surface of a semiconductor wafer including active areas and alignment mark trenches formed in the at least one alignment mark area; forming at least a second material layer over the first material layer including the active areas and the at least one alignment mark area; lithographically patterning and etching the at least a second material layer to form at least a plurality lines of the at least a second material layer adjacent to the alignment mark trenches; and, carrying out a CMP process to remove at least a portion of the at least a second material layer.

    摘要翻译： 一种用于在CMP工艺期间保护对准标记区域的方法，包括在半导体晶片的工艺表面上形成至少第一材料层，所述半导体晶片包括形成在所述至少一个对准标记区域中的有源区和对准标记沟槽; 在包括所述有源区域和所述至少一个对准标记区域的所述第一材料层上形成至少第二材料层; 对所述至少第二材料层进行光刻图案化和蚀刻，以形成与所述对准标记沟槽相邻的所述至少第二材料层的至少多条线; 以及执行CMP处理以去除所述至少第二材料层的至少一部分。

    Self-aligned implants to reduce cross-talk of imaging sensors
    12.
    发明授权
    Self-aligned implants to reduce cross-talk of imaging sensors 有权
    自对准植入物减少成像传感器的串扰

    公开(公告)号：US08367512B2

    公开(公告)日：2013-02-05

    申请号：US12871032

    申请日：2010-08-30

    申请人： Shih-Chi Fu ,  Kai Tzeng ,  Wen-Chen Lu

    发明人： Shih-Chi Fu ,  Kai Tzeng ,  Wen-Chen Lu

    IPC分类号： H01L21/331 ,  H01L21/02

    CPC分类号： H01L27/14887 ,  H01L21/76237 ,  H01L27/1463 ,  H01L27/14654 ,  H01L27/14672 ,  H01L27/14683 ,  H01L27/14689 ,  H01L31/18

    摘要： The embodiments of methods of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate described above enable reducing cross-talk (or blooming) of neighboring. The methods use an oxide implant mask to form a deep doped region and also to form a shallow doped region. In some embodiments, the shallow doped regions are narrower and are formed by depositing a conformal dielectric layer over the oxide implant mask to narrow the openings for implantation.

    摘要翻译： 在上述基板上的两个相邻传感器元件之间制备自对准隔离区域的方法的实施例能够减少相邻的串扰（或起霜）。 该方法使用氧化物注入掩模来形成深掺杂区域并且还形成浅掺杂区域。 在一些实施例中，浅掺杂区域较窄，并且通过在氧化物植入掩模上沉积保形介电层而形成，以缩小用于植入的开口。

    Self-aligned implants to reduce cross-talk of imaging sensors
    13.
    发明授权
    Self-aligned implants to reduce cross-talk of imaging sensors 有权
    自对准植入物减少成像传感器的串扰

    公开(公告)号：US09171876B2

    公开(公告)日：2015-10-27

    申请号：US14291384

    申请日：2014-05-30

    申请人： Shih-Chi Fu ,  Kai Tzeng ,  Wen-Chen Lu

    发明人： Shih-Chi Fu ,  Kai Tzeng ,  Wen-Chen Lu

    IPC分类号： H01L21/02 ,  H01L21/331 ,  H01L27/146 ,  H01L21/762 ,  H01L31/18

    CPC分类号： H01L27/14887 ,  H01L21/76237 ,  H01L27/1463 ,  H01L27/14654 ,  H01L27/14672 ,  H01L27/14683 ,  H01L27/14689 ,  H01L31/18

    摘要： A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region.

    摘要翻译： 一种在衬底上的两个相邻传感器元件之间制备自对准隔离区域的方法。 该方法包括图案化氧化物层以在衬底上的两个相邻传感器元件之间形成开口。 所述方法还包括执行第一注入以在所述两个相邻的传感器元件之间形成深掺杂区域并且从所述衬底的顶表面下方的距离开始。 该方法还包括执行第二植入以在两个相邻传感器元件之间形成浅掺杂区域，其中浅掺杂区域的底部与深掺杂区域的顶部部分重叠。

    Dummy gate structure for semiconductor devices
    14.
    发明授权
    Dummy gate structure for semiconductor devices 有权
    半导体器件的虚拟门结构

    公开(公告)号：US09136349B2

    公开(公告)日：2015-09-15

    申请号：US13345059

    申请日：2012-01-06

    申请人： Shih-Chi Fu ,  Chien-Chih Chou

    发明人： Shih-Chi Fu ,  Chien-Chih Chou

    IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/762

    CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/0207 ,  H01L29/66606

    摘要： A structure and method for fabricating a spacer structure for semiconductor devices, such as a multi-gate structure, is provided. The dummy gate structure is formed by depositing a dielectric layer, forming a mask over the dielectric layer, and patterning the dielectric layer. The mask is formed to have a tapered edge. In an embodiment, the tapered edge is formed in a post-patterning process, such as a baking process. In another embodiment, a relatively thick mask layer is utilized such that during patterning a tapered results. The profile of the tapered mask is transferred to the dielectric layer, thereby providing a tapered edge on the dielectric layer.

    摘要翻译： 提供了一种用于制造诸如多栅极结构的半导体器件的间隔结构的结构和方法。 虚拟栅极结构通过沉积介电层，在电介质层上形成掩模和图案化电介质层而形成。 掩模形成为具有锥形边缘。 在一个实施例中，锥形边缘在诸如烘烤工艺的后图案化工艺中形成。 在另一个实施例中，使用相对厚的掩模层，使得在图案化期间形成锥形结果。 锥形掩模的轮廓转移到电介质层，从而在电介质层上提供锥形边缘。

    Manufacturing techniques for workpieces with varying topographies
    15.
    发明授权
    Manufacturing techniques for workpieces with varying topographies 有权
    具有不同形貌的工件的制造技术

    公开(公告)号：US08771534B2

    公开(公告)日：2014-07-08

    申请号：US13350010

    申请日：2012-01-13

    申请人： Chun-Chang Chen ,  Shih-Chi Fu ,  Wang-Pen Mo ,  Hung-Chang Hsieh

    发明人： Chun-Chang Chen ,  Shih-Chi Fu ,  Wang-Pen Mo ,  Hung-Chang Hsieh

    IPC分类号： B44C1/22

    CPC分类号： H01L21/0276 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823456

    摘要： Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.

    摘要翻译： 一些实施例涉及用于处理工件的方法。 在该方法中，在工件上方设有抗反射涂层。 具有第一光致抗蚀剂色调的第一图案化光致抗蚀剂层设置在抗反射涂层上。 在第一图案化光致抗蚀剂层上提供具有与第一光致抗蚀剂色调相反的第二光致抗蚀剂色调的第二图案化光致抗蚀剂层。 开口延伸穿过第一和第二图案化的光致抗蚀剂层，以允许通过开口对工件施加处理。 还公开了其他实施例。

    Semiconductor devices and manufacturing methods thereof
    16.
    发明授权
    Semiconductor devices and manufacturing methods thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US08692296B2

    公开(公告)日：2014-04-08

    申请号：US13370132

    申请日：2012-02-09

    申请人： Chun-Chang Chen ,  Shun-Shing Yang ,  Shih-Chi Fu ,  Wang-Pen Mo ,  Hung-Chang Hsieh

    发明人： Chun-Chang Chen ,  Shun-Shing Yang ,  Shih-Chi Fu ,  Wang-Pen Mo ,  Hung-Chang Hsieh

    IPC分类号： H01L27/118 ,  H01L21/20

    CPC分类号： H01L21/823437 ,  H01L21/0274 ,  H01L21/32139 ,  H01L27/1052

    摘要： Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less.

    摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，半导体器件包括具有多个第一特征的第一区域的工件和具有靠近第一区域的多个第二特征的第二区域。 第一区域和第二区域共享布置在第一区域和第二区域之间的图案化重叠区域。 图案重叠区域包括长宽比为约4或更小的残留特征。

    Card edge connector
    17.
    发明授权
    Card edge connector 有权
    卡缘连接器

    公开(公告)号：US07713079B2

    公开(公告)日：2010-05-11

    申请号：US12494175

    申请日：2009-06-29

    申请人： Shih-Chi Fu

    发明人： Shih-Chi Fu

    IPC分类号： H01R13/62

    CPC分类号： H01R12/721 ,  H01R12/7029

    摘要： A card edge connector includes an insulating body having opposite lateral side frames for mounting respectively two metallic pieces thereon, and terminals mounted in the insulating body and coupled to a circuit board. When an insertion side with conductive terminals of an electronic card is inserted into an insertion groove in the insulating body, the conductive terminals contact respectively contact portions of the terminals extending into the insertion groove. Each metallic piece includes first and second resilient arms extending from a base, and a carved metallic piece extending from the first resilient arm. When the insertion side of the electronic card is inserted into the insertion groove, each lateral side of the electronic card is clamped between the anchoring member and the second resilient arm of a corresponding metallic piece, and is formed with a notch engaging a projection of the second resilient arm of the corresponding metallic piece.

    摘要翻译： 卡边缘连接器包括具有相对的侧边框架的绝缘体，用于在其上分别安装两个金属件，以及安装在绝缘体中并连接到电路板的端子。 当将具有电子卡的导电端子的插入侧插入绝缘体中的插入槽中时，导电端子分别接触延伸到插入槽中的端子的接触部分。 每个金属件包括从基座延伸的第一和第二弹性臂和从第一弹性臂延伸的雕刻金属片。 当电子卡的插入侧插入到插入槽中时，电子卡的每个横向侧被夹持在相应金属片的锚定构件和第二弹性臂之间，并且形成有凹口，该凹口与 相应金属片的第二弹性臂。