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    BOLOMETRIC ON-CHIP TEMPERATURE SENSOR
    12.
    发明申请
    BOLOMETRIC ON-CHIP TEMPERATURE SENSOR 失效
    BOLOMETRIC片上温度传感器

    公开(公告)号：US20090110023A1

    公开(公告)日：2009-04-30

    申请号：US12348974

    申请日：2009-01-06

    申请人： William F. Clark, JR. ,  Edward J. Nowak

    发明人： William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： G01K7/00 ,  G01K15/00

    CPC分类号： G01K7/015 ,  G01K7/22 ,  G01K15/00

    摘要： Disclosed are embodiments of an improved on-chip temperature sensing circuit, based on bolometry, which provides self calibration of the on-chip temperature sensors for ideality and an associated method of sensing temperature at a specific on-chip location. The circuit comprises a temperature sensor, an identical reference sensor with a thermally coupled heater and a comparator. The comparator is adapted to receive and compare the outputs from both the temperature and reference sensors and to drive the heater with current until the outputs match. Based on the current forced into the heater, the temperature rise of the reference sensor can be calculated, which in this state, is equal to that of the temperature sensor.

    摘要翻译： 公开了一种改进的片上温度感测电路的实施例，其基于速率测量，其提供用于理想的片上温度传感器的自校准以及在特定片上位置处感测温度的相关联的方法。 该电路包括温度传感器，具有热耦合加热器的相同参考传感器和比较器。 比较器适用于接收和比较来自温度和参考传感器的输出，并用电流驱动加热器直到输出匹配。 基于被迫进入加热器的电流，可以计算参考传感器的温度上升，在该状态下，其温度等于温度传感器的温升。

    CONTACT BARS FOR MODIFYING STRESS IN SEMICONDUCTOR DEVICE AND RELATED METHOD
    13.
    发明申请
    CONTACT BARS FOR MODIFYING STRESS IN SEMICONDUCTOR DEVICE AND RELATED METHOD 审中-公开
    用于修改半导体器件中的应力的接触棒及相关方法

    公开(公告)号：US20130240997A1

    公开(公告)日：2013-09-19

    申请号：US13424319

    申请日：2012-03-19

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L27/1104 ,  H01L29/7843

    摘要： Solutions for forming stress optimizing contact bars and contacts are disclosed. In one aspect, a semiconductor device is disclosed including an n-type field effect transistor (NFET) having source/drain regions; a p-type field effect transistor (PFET) having source/drain regions; a stress inducing layer over both the NFET and the PFET, the stress inducing layer inducing only one of a compressive stress and a tensile stress; a contact bar extending through the stress inducing layer and coupled to at least one of the source/drain regions of a selected device of the PFET and the NFET to modify a stress induced in the selected device compared to a stress induced in the other device; and a round contact extending through the stress inducing layer and coupled to at least one of the source/drain regions of the other device of the PFET and the NFET.

    摘要翻译： 公开了用于形成应力优化接触棒和触点的解决方案。 一方面，公开了一种具有源极/漏极区域的n型场效应晶体管（NFET）的半导体器件; 具有源极/漏极区域的p型场效应晶体管（PFET） 在NFET和PFET两者上的应力诱导层，应力诱导层仅引起压缩应力和拉伸应力之一; 接触棒延伸穿过应力感应层并且耦合到PFET和NFET的所选器件的源/漏区中的至少一个，以修改与在另一器件中感应的应力相比在所选器件中感应的应力; 以及延伸穿过应力感应层并且耦合到PFET和NFET的另一个器件的源极/漏极区域中的至少一个的圆形接触。

    SEMICONDUCTOR STRUCTURE WITH FIELD SHIELD AND METHOD OF FORMING THE STRUCTURE
    15.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH FIELD SHIELD AND METHOD OF FORMING THE STRUCTURE 有权
    具有现场屏蔽的半导体结构和形成结构的方法

    公开(公告)号：US20100047972A1

    公开(公告)日：2010-02-25

    申请号：US12610563

    申请日：2009-11-02

    申请人： William F. Clark, JR. ,  Edward J. Nowak

    发明人： William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： H01L21/336 ,  H01L21/762

    CPC分类号： H01L29/861 ,  H01L29/402 ,  H01L29/417 ,  H01L29/6609 ,  H01L29/772 ,  H01L29/78648

    摘要： Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate.

    摘要翻译： 公开了在半导体器件（例如场效应晶体管（FET）或二极管）之下并入场屏蔽的半导体结构。 场屏蔽被夹在晶片上的上隔离层和下隔离层之间。 局部互连延伸穿过上隔离层并将场屏蔽连接到器件的选定掺杂半导体区域（例如，FET的二极管的源极/漏极区域或二极管的阴极或阳极）。 进入设备的电流，例如，在线路充电的后端，被远离上隔离层的局部互连分流，并进入场屏蔽。 因此，不允许在上部隔离层中积聚电荷，而是从场屏蔽件渗入下部隔离层并进入下面的基板。 该场屏蔽进一步提供抵抗掉在下隔离层或衬底内的任何电荷的保护屏障。

    BIPOLAR TRANSISTOR AND BACK-GATED TRANSISTOR STRUCTURE AND METHOD
    16.
    发明申请
    BIPOLAR TRANSISTOR AND BACK-GATED TRANSISTOR STRUCTURE AND METHOD 有权
    双极晶体管和后置栅极结构和方法

    公开(公告)号：US20090298250A1

    公开(公告)日：2009-12-03

    申请号：US12536636

    申请日：2009-08-06

    申请人： Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    发明人： Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： H01L21/331

    CPC分类号： H01L21/84 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0804 ,  H01L29/7327 ,  H01L29/78648

    摘要： A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region, and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material. A method of forming the structures including a bipolar transistor and back-gated transistor together is also disclosed.

    摘要翻译： 公开了一种结构，其包括在体层上包括绝缘体层的衬底和在衬底的第一区域中的双极晶体管，所述双极晶体管包括绝缘体层中的发射极区域的至少一部分。 另一公开的结构包括在衬底的第一区域中的反相双极晶体管，其包括体层上的绝缘体层，反相双极晶体管包括发射极区域，以及位于衬底的第二区域中的后栅极晶体管，其中背面 背栅式晶体管的栅极导体和发射极区域的至少一部分处于相同的材料层中。 还公开了一种将双极晶体管和后栅极晶体管组合在一起的结构的方法。

    ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
    17.
    发明申请
    ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 有权
    不对称场效应晶体管结构与方法

    公开(公告)号：US20090020806A1

    公开(公告)日：2009-01-22

    申请号：US11778185

    申请日：2007-07-16

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/76

    CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7835

    摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

    摘要翻译： 公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供 改进的驱动电流，电路延迟最小）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定电容值）。

    INTEGRATED CIRCUIT INCLUDING TRANSISTOR STRUCTURE ON DEPLETED SILICON-ON-INSULATOR, RELATED METHOD AND DESIGN STRUCTURE
    18.
    发明申请
    INTEGRATED CIRCUIT INCLUDING TRANSISTOR STRUCTURE ON DEPLETED SILICON-ON-INSULATOR, RELATED METHOD AND DESIGN STRUCTURE 有权
    集成电路，包括在绝缘体上的晶体管结构，相关方法和设计结构

    公开(公告)号：US20140021547A1

    公开(公告)日：2014-01-23

    申请号：US13553947

    申请日：2012-07-20

    申请人： William F. Clark, JR. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

    发明人： William F. Clark, JR. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

    IPC分类号： H01L27/088 ,  H01L21/265

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.

    摘要翻译： 一种集成电路（IC）及其制造方法。 在一个实施例中，IC包括：衬底; 设置在所述基板上的第一半导体层; 在所述衬底的一部分内延伸穿过所述第一半导体层的浅沟槽隔离（STI），所述STI基本上分离第一n +区和第二n +区; 以及设置在所述第一半导体层的与所述STI连接的部分上的栅极，所述栅极包括：设置在所述第一半导体层上并连接到所述STI的掩埋金属氧化物（BOX）层; 设置在BOX层上的盖层; 以及设置在第一半导体层和衬底内的p型阱组件，p型阱组件连接到第二n +区。

    METHODS OF CHANGING THRESHOLD VOLTAGES OF SEMICONDUCTOR TRANSISTORS BY ION IMPLANTATION
    19.
    发明申请
    METHODS OF CHANGING THRESHOLD VOLTAGES OF SEMICONDUCTOR TRANSISTORS BY ION IMPLANTATION 有权
    通过离子注入改变半导体晶体管的阈值电压的方法

    公开(公告)号：US20090124069A1

    公开(公告)日：2009-05-14

    申请号：US11939578

    申请日：2007-11-14

    申请人： William F. Clark, JR. ,  Edward Joseph Nowak

    发明人： William F. Clark, JR. ,  Edward Joseph Nowak

    IPC分类号： H01L21/265

    CPC分类号： H01L21/26586 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/66795 ,  H01L29/66803

    摘要： A method for forming a semiconductor structure. The method includes providing a semiconductor structure including a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) a semiconductor body region. The method further includes implanting an adjustment dose of dopants of a first doping polarity into the semiconductor body region by an adjustment implantation process. Ion bombardment of the adjustment implantation process is in the reference direction. The method further includes (i) patterning the semiconductor substrate resulting in side walls of the semiconductor body region being exposed to a surrounding ambient and then (ii) implanting a base dose of dopants of a second doping polarity into the semiconductor body region by a base implantation process. Ion bombardment of the base implantation process is in a direction which makes a non-zero angle with the reference direction.

    摘要翻译： 一种形成半导体结构的方法。 该方法包括提供包括半导体衬底的半导体结构。 半导体衬底包括（i）限定垂直于顶部衬底表面的参考方向的顶部衬底表面和（ii）半导体本体区域。 该方法还包括通过调整注入工艺将第一掺杂极性的掺杂剂的调整剂量注入到半导体体区域中。 离子轰击调整植入过程在参考方向。 该方法还包括（i）对半导体衬底进行图形化，导致半导体体区域的侧壁暴露于周围环境，然后（ii）将碱性剂量的第二掺杂极性掺杂剂注入到半导体本体区域中， 植入过程。 基极注入工艺的离子轰击在与参考方向成非零角度的方向上。