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公开(公告)号：US20190156899A1
公开(公告)日：2019-05-23
申请号：US16192775
申请日：2018-11-15
Applicant: Winbond Electronics Corp.
Inventor： Kazuki Yamauchi , Makoto Senoo , Hiroki Murakami
Abstract: A semiconductor storage device with a smaller chip size than prior art and a readout method are provided. The semiconductor storage device includes a memory cell array; a page buffer/sense circuit having a sensing node for sensing readout data from a selected page of the memory cell array and a latch circuit for holding data sensed by the sensing node; and a controller controls operations on the memory cell array. The sensing node includes an NMOS capacitor.
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公开(公告)号：US10096369B2
公开(公告)日：2018-10-09
申请号：US15611791
申请日：2017-06-02
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami , Makoto Senoo
Abstract: A semiconductor device including a voltage generation circuit, and voltage generation circuit generates a required voltage according to internal data requested in response to an operation are provided. The voltage generating circuit includes a plurality of registers A-1, B-1, C-1, D-1, voltage generating blocks A-2, B-2, C-2 and a voltage switch. The registers A-1, B-1, C-1, D-1 hold data provided from control logic. The voltage generating blocks A-2, B-2, C-2 generate voltage based on voltage control data held by the registers A-1, B-1, C-1. The voltage switch selects voltages based on selection control data held by the register D-1. The connecting element includes signal lines for sequentially transmitting the voltage control data or the selection control data, signal lines for sequentially transmitting a clock signal CLK and signal lines for controlling output of data held by the registers.
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公开(公告)号：US20150055418A1
公开(公告)日：2015-02-26
申请号：US14301344
申请日：2014-06-11
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami , Kenichi Arakawa
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/28 , G11C16/30
Abstract: The invention provides a clamp voltage generating circuit capable of generating a correct clamp voltage. The clamp voltage generating circuit includes an emulate transistor, having a drain coupled to a power source VDD, a source coupled to a node, and a gate coupled to the clamp voltage; a current setting circuit, connected between the node and ground, for setting a current flowing from the node to the ground; a regulator, inputting a feedback voltage from the node and a reference voltage, and outputting a voltage VCLMP. The current setting circuit duplicates a current of a bit line, so that the emulate transistor is similar to a charge transfer transistor.
Abstract translation: 本发明提供一种能产生正确钳位电压的钳位电压发生电路。 钳位电压产生电路包括仿真晶体管，其具有耦合到电源VDD的漏极，耦合到节点的源极和耦合到钳位电压的栅极; 连接在节点和地之间的电流设定电路，用于设定从节点流向地面的电流; 调节器，输入来自节点的反馈电压和参考电压，并输出电压VCLMP。 电流设置电路复制位线的电流，使得仿真晶体管类似于电荷转移晶体管。
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公开(公告)号：US12032396B2
公开(公告)日：2024-07-09
申请号：US17846017
申请日：2022-06-22
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami
IPC: G05F1/565
CPC classification number: G05F1/565
Abstract: Disclosed is a voltage generating circuit including a reference voltage generating part, a leakage current monitoring part, a control part, and an internal voltage generating part. The reference voltage generating part generates a reference voltage. The leakage current monitoring part generates a monitoring leakage current corresponding to a leakage current of an internal circuit of a semiconductor device. The control part controls the reference voltage according to the monitoring leakage current. The internal voltage generating part receives the reference voltage being controlled by the control part, and supplies an internal voltage to the internal circuit according to the controlled reference voltage. A semiconductor device including the same is also disclosed.
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公开(公告)号：US20170365325A1
公开(公告)日：2017-12-21
申请号：US15613285
申请日：2017-06-05
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami
IPC: G11C11/408 , G11C8/14 , G11C8/08 , G11C11/4074 , G11C11/56 , G11C11/4099
CPC classification number: G11C11/4085 , G11C8/08 , G11C8/14 , G11C11/4074 , G11C11/4082 , G11C11/4099 , G11C11/5621 , G11C16/0483 , G11C16/08 , G11C16/30
Abstract: A non-volatile semiconductor memory device and a driving method for word lines thereof are provided. A flash memory of the invention includes a memory cell array including blocks and a block selection element selecting the block of the memory cell array based on row address information and including a block selection transistor, a level shifter, a boost circuit and a voltage supplying element. The block selection transistor is connected to each word line of the block. The level shifter supplies a voltage to a node connected to a gate of the block selection transistor. The boost circuit boosts a potential of the node. The voltage supplying element supplies an operation voltage to one of the terminals of the block selection transistor. The node, after performing first boosting by the operating voltage supplied by the supplying element, performs second boosting by the second circuit.
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Patent Agency Ranking
公开(公告)号：US09501354B2
公开(公告)日：2016-11-22
申请号：US14619639
申请日：2015-02-11
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami
CPC classification number: G06F11/1048 , G11C2029/0411
Abstract: A semiconductor memory device includes: a memory array; a data-maintaining component, maintaining data read from the memory array or maintaining data used for writing to the memory array; an external input/output terminal; an error correction component, coupling the data-maintaining component and performing error-detection or correcting the data input to the data-maintaining component or output data from the data-maintaining component; a compressing component, coupling between the external input/output terminal and the error correction component and compressing or extending data. The compressing component compresses data provided by the external input/output terminal, provides the compressed data to the error correction component, extends the data provided by the error correction component, and provides the extended data to the external input/output terminal.
Abstract translation: 半导体存储器件包括：存储器阵列; 数据维护组件，保持从存储器阵列读取的数据或维护用于写入存储器阵列的数据; 外部输入/输出端子; 耦合数据维护组件并执行错误检测或校正数据输入到数据维护组件或从数据维护组件输出数据; 压缩部件，外部输入/输出端子与纠错部件之间的耦合以及压缩或扩展数据。 压缩组件压缩由外部输入/输出终端提供的数据，将压缩数据提供给纠错组件，扩展由纠错组件提供的数据，并将扩展数据提供给外部输入/输出终端。
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公开(公告)号：US11323067B2
公开(公告)日：2022-05-03
申请号：US17235270
申请日：2021-04-20
Applicant: Winbond Electronics Corp.
Inventor： Masafumi Nakatani , Hiroki Murakami
IPC: H03B5/04 , G05F3/26 , H03K3/0232 , H03K3/011 , H03K3/0231 , G05F1/573 , H03K5/135 , G05F1/56
Abstract: The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.
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18.发明授权公开(公告)号：US10978162B2
公开(公告)日：2021-04-13
申请号：US16800369
申请日：2020-02-25
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami
Abstract: A protection method is provided to make it difficult to reverse engineer operational information. The present invention provides a protection method for preventing reverse engineering, including: generating an expected value during normal operation; monitoring voltage waveforms at monitoring points of the semiconductor integrated circuit; comparing a measured value generated in the monitored voltage waveforms with the expected value; determining whether reverse engineering is taking place or not based on comparison results; and when reverse engineering is taking place, controlling the semiconductor integrated circuit to run in a protection mode, which different from its normal operation.
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公开(公告)号：US10972005B2
公开(公告)日：2021-04-06
申请号：US16743324
申请日：2020-01-15
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami
Abstract: A charge pump circuit that suppresses low boost efficiency is provided. The charge pump circuit 100 of the invention includes a main pump circuit CPn_M and a gate controlling pump circuit CPn_G controlling the main pump circuit CPn_M. The main pump circuit has the same basic configuration as the controlling pump circuit, which are both KER-type pump circuits. The controlling pump circuit controls the operation of a transistor of the main pump circuit after the main pump circuit is boosted, so that reverse current will not flow from the main pump circuit to the forward section of the pump circuit.
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公开(公告)号：US10726927B2
公开(公告)日：2020-07-28
申请号：US16231402
申请日：2018-12-22
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami
Abstract: A voltage generation circuit, having a circuit scale significantly reduced as compared with the related art, is provided. The voltage generation circuit of the disclosure includes a charge pump outputting a boosted voltage to an output node, a resistor connected between the output node and another output node, and a current source circuit having first and second current paths connected in parallel between the another output node and a reference potential. The first current path includes a resistor and a first DAC. The first DAC generates a first constant current corresponding to a voltage generation code. The second current path includes a second DAC. The second DAC generates a second constant current corresponding to a code obtained by inverting the voltage generation code. Thereby, a driving voltage obtained by lowering the boosted voltage is generated at the other output node.
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