公开(公告)号：US20070038848A1

公开(公告)日：2007-02-15

申请号：US11446020

申请日：2006-06-02

申请人： Michael Gschwind ,  Robert Montoye ,  Brett Olsson ,  John-David Wellman

发明人： Michael Gschwind ,  Robert Montoye ,  Brett Olsson ,  John-David Wellman

IPC分类号： G06F9/44

CPC分类号： G06F9/3012 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3885

摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.

摘要翻译： 提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。 一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理固定宽度指令集的固定宽度指令。 固定宽度指令包括不连续的寄存器说明符。

公开(公告)号：US20060208763A1

公开(公告)日：2006-09-21

申请号：US11082805

申请日：2005-03-17

申请人： Hung Ngo ,  Jayakumaran Sivagnaname ,  Kevin Nowka ,  Robert Montoye

发明人： Hung Ngo ,  Jayakumaran Sivagnaname ,  Kevin Nowka ,  Robert Montoye

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.

摘要翻译： 只要电路处于活动模式，LSDL电路用动态节点的预充电装置的正常时钟控制替代逻辑零的控制信号，并且当电路处于待机模式时，逻辑为逻辑1。 预充电装置将动态节点保持在与时钟无关的预充电逻辑1状态。 在逻辑1期间评估时钟的时间，逻辑树确定动态节点的断言状态。 在评估时间期间，断言状态由静态LSDL部分锁存。 然后动态节点重新充电到预充电状态。 由于在评估时间期间预充电装置没有被去门，所以动态节点不能被无意中的噪声放电，导致错误。 类似地，由于时钟不耦合到预充电装置，所以从时钟树中降低时钟功率的负载被去除。

公开(公告)号：US20070038984A1

公开(公告)日：2007-02-15

申请号：US11446031

申请日：2006-06-02

申请人： Michael Gschwind ,  Robert Montoye ,  Brett Olsson ,  John-David Wellman

发明人： Michael Gschwind ,  Robert Montoye ,  Brett Olsson ,  John-David Wellman

IPC分类号： G06F9/45

CPC分类号： G06F8/447

摘要： There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

摘要翻译： 提供了用于为编码扩展寄存器规范的架构生成代码的方法和计算机程序产品。 用于生成固定宽度指令集的代码的方法包括识别不连续的寄存器说明符。 该方法还包括生成包括非连续寄存器说明符的固定宽度指令字。

公开(公告)号：US20060179096A1

公开(公告)日：2006-08-10

申请号：US11055232

申请日：2005-02-10

申请人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Robert Montoye ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

发明人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Robert Montoye ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/49947 ,  G06F7/5443

摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes computer instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.

摘要翻译： 一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。 该系统还包括用于响应于确定操作数是单精度来执行操作数的单精度递增的计算机指令，操作数基于先前操作的结果需要增加，并且先前的操作未执行递增。 操作数是在以前的操作中创建的。 该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

公开(公告)号：US20060027934A1

公开(公告)日：2006-02-09

申请号：US11242221

申请日：2005-10-03

申请人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker ,  Yu-Ting Cheng ,  Kenneth Ocheltree ,  Robert Montoye

发明人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker ,  Yu-Ting Cheng ,  Kenneth Ocheltree ,  Robert Montoye

IPC分类号： H01L23/48

CPC分类号： H01L23/49883 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

公开(公告)号：US20060020863A1

公开(公告)日：2006-01-26

申请号：US10896505

申请日：2004-07-22

申请人： Andrew Martin ,  Chandler McDowell ,  Robert Montoye ,  Jun Sawada

发明人： Andrew Martin ,  Chandler McDowell ,  Robert Montoye ,  Jun Sawada

IPC分类号： G01R31/28

CPC分类号： G11C29/32 ,  G01R31/318572 ,  G11C11/41 ,  G11C2029/3202

摘要： A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By turning on the transistor, the contents of the latch can be selectively read or written to.

摘要翻译： 一种用于从锁存器的矩阵阵列中的特定锁存器扫描数据的方法和系统。 矩阵阵列由垂直选择线和水平数据线组成。 每个锁存器通过晶体管耦合在选择器线和数据线的交叉点处。 通过接通晶体管，可以选择性地读取或写入锁存器的内容。

公开(公告)号：US20050102346A1

公开(公告)日：2005-05-12

申请号：US10702992

申请日：2003-11-06

申请人： Wendy Belluomini ,  Ramyanshu Datta ,  Jente Kuang ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

发明人： Wendy Belluomini ,  Ramyanshu Datta ,  Jente Kuang ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

IPC分类号： G06F7/50 ,  G06F7/60

CPC分类号： G06F7/607

摘要： A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.

摘要翻译： 一个4对2进位存储加法器，减少输出和输入位的延迟。 4对2进位存储加法器可以包括耦合到较高阶全加器的较低阶满载。 进位保存加法器还可以包括耦合到高阶全加器的逻辑单元，其中逻辑单元被配置为产生要输入到通常将从位于该位置的进位保存加法器产生的高阶全加器的进位位 前一阶段 通过在当前阶段而不是在前一阶段生成该进位位（进位位），减少输入到较高阶全加器的进位位的延迟，从而减少输出和和输出位的延迟 由高阶全加器。

公开(公告)号：US08446748B2

公开(公告)日：2013-05-21

申请号：US13198292

申请日：2011-08-04

申请人： Chung Hon Lam ,  Jing Li ,  Robert Montoye

发明人： Chung Hon Lam ,  Jing Li ,  Robert Montoye

IPC分类号： G11C15/04

CPC分类号： G06F17/5077 ,  G11C5/06 ,  G11C11/412 ,  G11C15/04

摘要： What is disclosed is a novel memory array and process for creating a memory array to reduce wireline variability. The method includes accessing a routing design of a memory array with a plurality of memory cells. Each memory cell in the array includes one or more access devices, and a group of wires electrically connected between one or more of the memory cells and peripheral circuitry (PC). The group of the group of wires is divided into at least one subgroup (N). Next, a capacitance (C1, C2 . . . CN) of each wire in the subgroup (N) is calculated. Continuing further, a maximum capacitance (CMAX) of wires in the subgroup (N) is determined. An add-on capacitance to be added to a number (NA) of the wires in the subgroup (N) is calculated.

摘要翻译： 公开的是一种新颖的存储器阵列和用于创建存储器阵列以减少有线变化的过程。 该方法包括使用多个存储器单元访问存储器阵列的路由设计。 阵列中的每个存储单元包括一个或多个访问设备，以及电连接在一个或多个存储器单元和外围电路（PC）之间的一组电线。 该组电线分为至少一个子组（N）。 接下来，计算子组（N）中每根导线的电容（C1，C2 ... CN）。 进一步地，确定子组（N）中的导线的最大电容（CMAX）。 计算要添加到子组（N）中的数量（NA）的附加电容。

公开(公告)号：US20070130237A1

公开(公告)日：2007-06-07

申请号：US11295300

申请日：2005-12-06

申请人： Erik Altman ,  Michael Gschwind ,  Robert Montoye ,  Jude Rivers ,  Sumedh Sathaye ,  John-David Wellman ,  Victor Zyuban

发明人： Erik Altman ,  Michael Gschwind ,  Robert Montoye ,  Jude Rivers ,  Sumedh Sathaye ,  John-David Wellman ,  Victor Zyuban

IPC分类号： G06F17/30

CPC分类号： G06F12/1491 ,  G06F9/3808 ,  G06F9/3844 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/12

摘要： A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage. This transient storage scheme allows the cache hierarchy to store data items that may be used by the processor core but that may be too expensive to allocate to external memory.

摘要翻译： 公开了一种用于存储非关键处理器信息而不对处理器设计造成重大成本的方法和装置。 瞬态数据存储在处理器本地缓存层次结构中。 附加控制位构成高速缓存地址的一部分，其中具有控制位置位的地址被指定为“瞬时存储地址”。 瞬态存储地址不会被写回外部主存储器，而当从最后一级高速缓存驱逐时，它们将被丢弃。 优选地，瞬态存储地址是“特权的”，因为它们不能被软件访问或只能具有具有适当权限的监督或管理员级软件访问。 提供了许多管理功能/指令，以允许管理员/管理软件管理和/或修改瞬态缓存存储的行为。 这种瞬态存储方案允许高速缓存层级来存储处理器核心可能使用的数据项，但是可能太昂贵以分配给外部存储器。

公开(公告)号：US20060107090A1

公开(公告)日：2006-05-18

申请号：US10977432

申请日：2004-10-29

申请人： Philip Emma ,  Robert Montoye ,  William Reohr

发明人： Philip Emma ,  Robert Montoye ,  William Reohr

IPC分类号： G06F11/00

CPC分类号： G06F12/0893 ,  G06F11/1064 ,  G06F2212/1056 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/4096 ,  G11C2029/0411 ,  G11C2207/2245 ,  G11C2211/4062 ,  Y02D10/13

摘要： Apparatus for passively tracking expired data in a dynamic memory includes an error encoding circuit operative to receive an input data word and to generate an encoded data word which is stored in the dynamic memory. The apparatus further includes a decoding circuit operative to receive an encoded data word from the dynamic memory, to detect at least one or more unidirectional errors in the input data word read from the dynamic memory, and to generate an error signal when at least one error is detected, the error signal indicating that the input data word contains expired data. Control circuitry included in the apparatus is configured for initiating one or more actions in response to the error signal.

摘要翻译： 用于在动态存储器中被动跟踪过期数据的装置包括错误编码电路，其操作以接收输入数据字并产生存储在动态存储器中的编码数据字。 该装置还包括一个解码电路，用于从动态存储器接收编码的数据字，以检测从动态存储器读取的输入数据字中的至少一个或多个单向错误，并且当至少一个错误 检测出指示输入数据字包含过期数据的错误信号。 包括在装置中的控制电路被配置为响应于该误差信号启动一个或多个动作。