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1.发明申请METHOD AND APPARATUS FOR FORMING STACKED DIE AND SUBSTRATE STRUCTURES FOR INCREASED PACKING DENSITY 有权用于形成堆叠的堆叠密度的堆叠式衬底和衬底结构的方法和装置公开(公告)号：US20060249827A1
公开(公告)日：2006-11-09
申请号：US10908277
申请日：2005-05-05
Applicant: Benjamin Fasano , Brian Sundlof
Inventor： Benjamin Fasano , Brian Sundlof
IPC: H01L23/02
CPC classification number: H01L25/0657 , H01L2224/16 , H01L2224/73253 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/16152 , H01L2924/1627 , H01L2924/3025 , H01L2224/0401
Abstract: A stacked semiconductor apparatus has at least one die attached to a first side of a carrier substrate. A first circuitized substrate is attached to the first side of the carrier substrate and overlying the at least one die in a manner such that the first circuitized substrate serves as an electrical interconnection device and a heat spreading lid. The first circuitized substrate is further configured so as to facilitate cooling of the at least one die by at least a cross flow of a cooling medium therethrough.
Abstract translation: 叠层半导体装置具有至少一个附着在载体基板的第一侧的管芯。 第一电路化基板被附接到载体基板的第一侧并且以使得第一电路化基板用作电互连装置和散热盖的方式覆盖至少一个管芯。 第一电路化基板被进一步构造成便于通过至少一个冷却介质的横流而使至少一个管芯冷却。
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公开(公告)号：US20060112857A1
公开(公告)日：2006-06-01
申请号：US10986665
申请日：2004-11-12
Applicant: Gareth Hougham , Paul Lauro , Brian Sundlof , Jeffrey Gelorme
Inventor： Gareth Hougham , Paul Lauro , Brian Sundlof , Jeffrey Gelorme
IPC: C09C1/44
CPC classification number: H01L23/3733 , B82Y30/00 , H01L23/373 , H01L23/3736 , H01L23/40 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , Y10S977/788 , Y10T156/10 , Y10T428/24994 , H01L2224/0401
Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.
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3.发明申请公开(公告)号：US20050148164A1
公开(公告)日：2005-07-07
申请号：US10707693
申请日：2004-01-05
Applicant: JON CASEY , BRIAN SUNDLOF
Inventor： JON CASEY , BRIAN SUNDLOF
IPC: H01L23/12 , H01B1/16 , H01L21/00 , H01L21/02 , H01L21/44 , H01L21/48 , H01L21/768 , H01L23/48 , H05K1/09 , H05K3/40 , H05K3/46
CPC classification number: H05K3/4061 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/09701 , H05K1/092 , H05K2201/068 , H01L2924/00012 , H01L2924/00
Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.
Abstract translation: 一种金属化工艺和材料系统，用于在硅中金属化盲孔或通孔，涉及相对于纯金属（例如铜，银或金）形成低热膨胀复合材料或悬浮系数，并填充硅中的通孔 用糊或悬浮液。 悬浮液以最小的体积收缩率烧结，形成高导电性结构，而不形成宏观空隙。 所选择的悬架保持更接近于硅的热膨胀系数。
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4.发明申请Silicon chip carrier with conductive through-vias and method for fabricating same 有权具有导电通孔的硅芯片载体及其制造方法公开(公告)号：US20050121768A1
公开(公告)日：2005-06-09
申请号：US10729254
申请日：2003-12-05
Applicant: Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker
Inventor： Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker
IPC: H01L21/48 , H01L21/768 , H01L23/498 , H01L23/48 , H01L21/4763
CPC classification number: H01L23/49883 , H01L21/486 , H01L21/76898 , H01L23/49827 , H01L2224/16 , H01L2924/01004 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
Abstract translation: 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。
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5.发明申请公开(公告)号：US20050100743A1
公开(公告)日：2005-05-12
申请号：US10702280
申请日：2003-11-06
Applicant: Gareth Hougham , Xiao Liu , S. Chey , James Doyle , Joseph Zinter , Michael Rooks , Brian Sundlof , Jon Casey
Inventor： Gareth Hougham , Xiao Liu , S. Chey , James Doyle , Joseph Zinter , Michael Rooks , Brian Sundlof , Jon Casey
CPC classification number: H01R13/2414 , B32B15/08 , H01R43/007 , H05K1/0271 , H05K3/321 , H05K3/325 , H05K2201/0218 , H05K2201/068 , Y10T428/12028 , Y10T428/12181 , Y10T428/12535 , Y10T428/249971 , Y10T428/249974 , Y10T428/31609
Abstract: A negative coefficient of thermal expansion particle includes a first bilayer having a first bilayer inner layer and a first bilayer outer layer, and a second bilayer having a second bilayer inner layer and a second bilayer outer layer. The first and second bilayers are joined together along perimeters of the first and second bilayer outer layers and first and second bilayer inner layers, respectively. The first bilayer inner layer and the second bilayer inner layer are made of a first material and the first bilayer outer layer and the second bilayer outer layer are made of a second material. The first material has a greater coefficient of thermal expansion than that of the second material.
Abstract translation: 负系数的热膨胀粒子包括具有第一双层内层和第一双层外层的第一双层和具有第二双层内层和第二双层外层的第二双层。 第一和第二双层分别沿着第一和第二双层外层以及第一和第二双层内层的周边连接在一起。 第一双层内层和第二双层内层由第一材料制成，第一双层外层和第二双层外层由第二材料制成。 第一种材料具有比第二种材料更大的热膨胀系数。
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Patent Agency Ranking
公开(公告)号：US20050176255A1
公开(公告)日：2005-08-11
申请号：US11099161
申请日：2005-04-05
Applicant: Jon Casey , James Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David Long , Lori Maiorino , Arthur Merryman , Glenn Pomerantz , Robert Rita , Krystyna Semkow , Patrick Spencer , Brian Sundlof , Richard Surprenant , Donald Wall , Thomas Wassick , Kathleen Wiley
Inventor： Jon Casey , James Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David Long , Lori Maiorino , Arthur Merryman , Glenn Pomerantz , Robert Rita , Krystyna Semkow , Patrick Spencer , Brian Sundlof , Richard Surprenant , Donald Wall , Thomas Wassick , Kathleen Wiley
IPC: H05K3/46 , H01L21/48 , H01L23/12 , H01L23/498 , H05K1/03 , H05K3/00 , H05K3/22 , H01L21/311 , H01L21/00 , H01L21/302 , H01L21/461 , H01L29/745 , H01L29/76
CPC classification number: H05K3/225 , H01L21/4846 , H01L23/49811 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0306 , H05K3/0029 , H05K3/4629 , H05K2203/173 , Y10T29/49124 , Y10T29/49135 , H01L2924/00
Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.
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公开(公告)号：US20050106834A1
公开(公告)日：2005-05-19
申请号：US10700327
申请日：2003-11-03
Applicant: Paul Andry , Jon Casey , Raymond Horton , Chiraq Patel , Edmund Sprogis , Brian Sundlof
Inventor： Paul Andry , Jon Casey , Raymond Horton , Chiraq Patel , Edmund Sprogis , Brian Sundlof
CPC classification number: H01L21/486 , H01L23/147 , H01L2224/16225 , H01L2924/10253 , H01L2924/1461 , H01L2924/15311 , H01L2924/00
Abstract: A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; and pressurizing the paste to fill the vias.
Abstract translation: 一种用于在晶片中填充通孔，特别是初始盲孔的方法，以及用于执行该方法的各种装置，包括从通孔排出空气; 捕获晶片的至少一部分和用于在两个表面之间填充通孔的糊状物; 并对该糊状物加压以填充通孔。
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8.发明申请METHOD AND APPARATUS FOR FORMING STACKED DIE AND SUBSTRATE STRUCTURES FOR INCREASED PACKING DENSITY 有权用于形成堆叠的堆叠密度的堆叠式衬底和衬底结构的方法和装置公开(公告)号：US20070196953A1
公开(公告)日：2007-08-23
申请号：US11740962
申请日：2007-04-27
Applicant: Benjamin Fasano , Brian Sundlof
Inventor： Benjamin Fasano , Brian Sundlof
IPC: H01L21/00
CPC classification number: H01L25/0657 , H01L2224/16 , H01L2224/73253 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/16152 , H01L2924/1627 , H01L2924/3025 , H01L2224/0401
Abstract: A stacked semiconductor apparatus has at least one die attached to a first side of a carrier substrate. A first circuitized substrate is attached to the first side of the carrier substrate and overlying the at least one die in a manner such that the first circuitized substrate serves as an electrical interconnection device and a heat spreading lid. The first circuitized substrate is further configured so as to facilitate cooling of the at least one die by at least a cross flow of a cooling medium therethrough.
Abstract translation: 叠层半导体装置具有至少一个附着在载体基板的第一侧的管芯。 第一电路化基板被附接到载体基板的第一侧并且以使得第一电路化基板用作电互连装置和散热盖的方式覆盖至少一个管芯。 第一电路化基板被进一步构造成便于通过至少一个冷却介质的横流而使至少一个管芯冷却。
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公开(公告)号：US20070032078A1
公开(公告)日：2007-02-08
申请号：US11544220
申请日：2006-10-10
Applicant: Jon Casey , Brian Sundlof
Inventor： Jon Casey , Brian Sundlof
IPC: H01L21/44
CPC classification number: H05K3/4061 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/09701 , H05K1/092 , H05K2201/068 , H01L2924/00012 , H01L2924/00
Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.
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10.发明申请Silicon chip carrier with conductive through-vias and method for fabricating same 审中-公开具有导电通孔的硅芯片载体及其制造方法公开(公告)号：US20060027934A1
公开(公告)日：2006-02-09
申请号：US11242221
申请日：2005-10-03
Applicant: Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker , Yu-Ting Cheng , Kenneth Ocheltree , Robert Montoye
Inventor： Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker , Yu-Ting Cheng , Kenneth Ocheltree , Robert Montoye
IPC: H01L23/48
CPC classification number: H01L23/49883 , H01L21/486 , H01L21/76898 , H01L23/49827 , H01L2224/16 , H01L2924/01004 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
Abstract translation: 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。
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