公开(公告)号：US20240120202A1

公开(公告)日：2024-04-11

申请号：US17961032

申请日：2022-10-06

Applicant: Wolfspeed, Inc.

Inventor： Scott Sheppard ,  Kyle Bothe ,  Chris Michael Hardiman

IPC: H01L21/265 ,  H01L21/225 ,  H01L21/74

CPC classification number: H01L21/26553 ,  H01L21/2253 ,  H01L21/74

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a semiconductor structure having a buried layer at a depth of about 275 Angstroms or greater (e.g., about 500 Angstroms or greater) from a surface of the semiconductor structure. The semiconductor device includes an implanted region extending at least partially through the semiconductor structure and into the buried layer. The implanted region includes a distribution of implanted dopants of a first conductivity type extending into the buried layer. The semiconductor device includes an electrode on the implanted region. In some examples, the semiconductor structure may include an N-polar Group III-nitride semiconductor structure.

公开(公告)号：US20230395670A1

公开(公告)日：2023-12-07

申请号：US17834144

申请日：2022-06-07

Applicant: Wolfspeed, Inc.

Inventor： Chris Hardiman ,  Kyoung-Keun Lee ,  Kyle Bothe ,  Fabian Radulescu

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/42316 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L21/28581 ,  H01L29/66462

Abstract: A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer; source and drain contacts on the semiconductor structure; and a gate on the semiconductor structure between the source and drain contacts. A first portion of the barrier layer extending between the source or drain contact and the gate has a first thickness, a second portion of the barrier layer between the gate and the channel layer has a second thickness, and the first thickness is about 1.5 times to 4 times greater than the second thickness. Related methods of fabrication using a looped recess process are also discussed.

公开(公告)号：US11749726B2

公开(公告)日：2023-09-05

申请号：US17325666

申请日：2021-05-20

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Jeremy Fisher ,  Matt King ,  Jia Guo ,  Qianli Mu ,  Scott Sheppard

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/404 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786

Abstract: A transistor device includes a semiconductor layer, source and drain contacts on the semiconductor layer, a gate contact on the semiconductor layer between the source and drain contacts, and a field plate over the semiconductor layer between the gate contact and the drain contact. The transistor device includes a first electrical connection between the field plate and the source contact that is outside an active region of the transistor device, and a second electrical connection between the field plate and the source contact.

公开(公告)号：US20250142918A1

公开(公告)日：2025-05-01

申请号：US18545517

申请日：2023-12-19

Applicant: Wolfspeed, Inc.

Inventor： Saptha Sriram ,  Kyle Bothe ,  Matt King ,  James Tweedie

IPC: H01L29/40 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L29/20 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778

Abstract: A transistor includes a group III-Nitride channel layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer having a higher bandgap than a bandgap of the group III-Nitride channel layer; a low resistance contact layer on the group III-Nitride barrier layer and/or on the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer. A drain electrically coupled to the group III-Nitride barrier layer; and a gate on the group III-Nitride barrier layer. Additionally, at least one of the drain and the source are arranged on the low resistance contact layer.

公开(公告)号：US20240063300A1

公开(公告)日：2024-02-22

申请号：US17890453

申请日：2022-08-18

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Chris Hardiman ,  Elizabeth Keenan ,  Jia Guo ,  Fabian Radulescu ,  Scott Sheppard

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/417

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/41725

Abstract: A high electron mobility transistor comprises a semiconductor layer structure that includes a channel layer and a barrier layer and source and drain contacts on the semiconductor layer structure. A gate contact and a multi-layer passivation structure are provided on the semiconductor layer structure between the source contact and the drain contact. The multi-layer passivation structure comprises at least first and second silicon nitride layers that have different material compositions. A spacer passivation layer is provided on sidewalls of the first and second silicon nitride layers. A material composition of the spacer passivation layer is different than a material composition of at least one of the layers of the multi-layer passivation structure.

公开(公告)号：US11791389B2

公开(公告)日：2023-10-17

申请号：US17144346

申请日：2021-01-08

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Jia Guo ,  Jeremy Fisher ,  Scott Sheppard

IPC: H01L29/417 ,  H01L23/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H03F3/195 ,  H03F3/213

CPC classification number: H01L29/41775 ,  H01L23/66 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H03F3/195 ,  H03F3/213 ,  H01L2223/6644 ,  H01L2223/6683 ,  H03F2200/451

Abstract: A gallium nitride-based RF transistor amplifier comprises a semiconductor layer structure comprising a barrier layer on a channel layer, first and second source/drain regions in the semiconductor layer structure, first and second source/drain contacts on the respective first and second source/drain regions, and a longitudinally-extending gate finger that is between the first and second source/drain contacts. The first and second source/drain contacts each has an inner sidewall that faces the gate finger and an opposed outer sidewall. The first source/drain region extends a first distance from a lower edge of the inner sidewall of the first source/drain contact towards the second source/drain region along a transverse axis that extends parallel to a plane defined by the upper surface of the semiconductor layer structure, and extends a second, smaller distance from a lower edge of the outer sidewall of the first source/drain contact away from the second source/drain region.

公开(公告)号：US20230261054A1

公开(公告)日：2023-08-17

申请号：US17669479

申请日：2022-02-11

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Chloe Hawes ,  Jennifer Gao ,  Scott Sheppard

IPC: H01L29/08 ,  H01L29/778 ,  H01L29/66 ,  H01L21/266 ,  H01L21/265

CPC classification number: H01L29/0891 ,  H01L21/266 ,  H01L21/26513 ,  H01L29/7786 ,  H01L29/66462

Abstract: A HEMT transistor has a semiconductor layer structure that comprises a Group III nitride-based channel layer and a higher bandgap Group III nitride-based barrier layer on the channel layer. A gate finger and first and second source/drain contacts are provided on the semiconductor layer structure. A first source/drain region is provided in the semiconductor layer structure that includes a first implanted region that is underneath the first source/drain contact and a first auxiliary implanted region. A depth of the first implanted region is at least twice a depth of the first auxiliary implanted a region. The first source/drain region extends inwardly a first distance from a lower edge of an inner sidewall of the first source/drain contact, and extends outwardly a second smaller distance from a lower edge of an outer sidewall of the first source/drain contact.

公开(公告)号：US11682634B2

公开(公告)日：2023-06-20

申请号：US17060540

申请日：2020-10-01

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Dan Namishia ,  Fabian Radulescu ,  Scott Sheppard

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/66 ,  H01L23/64 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/564 ,  H01L23/31 ,  H01L23/528 ,  H01L23/642 ,  H01L23/645 ,  H01L23/66 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/6683

Abstract: A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

公开(公告)号：US11658234B2

公开(公告)日：2023-05-23

申请号：US17325576

申请日：2021-05-20

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Terry Alcorn ,  Dan Namishia ,  Jia Guo ,  Matt King ,  Saptharishi Sriram ,  Jeremy Fisher ,  Fabian Radulescu ,  Scott Sheppard ,  Yueying Liu

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7786 ,  H01L29/402 ,  H01L29/66462

Abstract: A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, a source contact and a drain contact on the barrier layer, an insulating layer on the semiconductor layer between the source contact and the drain contact, and a gate contact on the insulating layer. The gate contact includes a central portion that extends through the insulating layer and contacts the barrier layer and a drain side wing that extends laterally from the central portion of the gate toward the drain contact by a distance ΓD. The drain side wing of the gate contact is spaced apart from the barrier layer by a distance d1 that is equal to a thickness of the insulating layer. The distance ΓD is less than about 0.3 μm, and the distance d1 is less than about 80 nm.

公开(公告)号：US20230130614A1

公开(公告)日：2023-04-27

申请号：US17508846

申请日：2021-10-22

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Evan Jones

IPC: H01L29/45 ,  H01L29/20 ,  H01L29/778

Abstract: A transistor includes a semiconductor layer and a channel region. The transistor further includes a first doped contact region in the semiconductor layer and adjacent the channel region. The transistor further includes a first ohmic contact including an interface region comprising a first interface length between the first ohmic contact and the first doped contact region larger than a length of the interface region.