公开(公告)号：US07511993B2

公开(公告)日：2009-03-31

申请号：US11724268

申请日：2007-03-15

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Beak-Hyung Cho ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Beak-Hyung Cho ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72

摘要： A phase change memory device comprises a memory cell array and a write driver circuit. The memory cell array comprises a plurality of memory cells, and the write driver circuit comprises a set current driver and a reset current driver. The set current driver is adapted to provide a set current to a selected memory cell among the plurality of memory cells and the reset current driver is adapted to provide a reset current to a selected memory cell among the plurality of memory cells.

摘要翻译： 相变存储器件包括存储单元阵列和写入驱动器电路。 存储单元阵列包括多个存储单元，并且写驱动器电路包括设定电流驱动器和复位电流驱动器。 所设置的电流驱动器适于向所述多个存储器单元中的所选择的存储单元提供设定电流，并且所述复位电流驱动器适于向所述多个存储器单元中的所选存储单元提供复位电流。

公开(公告)号：US20070217273A1

公开(公告)日：2007-09-20

申请号：US11616969

申请日：2006-12-28

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hye-Jin Kim

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hye-Jin Kim

IPC分类号： G11C29/00

CPC分类号： G11C29/808 ,  G11C29/02 ,  G11C29/027 ,  G11C29/787 ,  G11C29/804 ,  G11C29/846

摘要： A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.

摘要翻译： 相变随机存取存储器包括存储块，该存储块包括对应于同一列地址的多个存储器列并使用不同的输入/输出路径; 冗余存储器块，其包括使用不同的输入/输出路径的多个冗余存储器列; 以及输入/输出控制器，其使用所述多个冗余存储器列中的至少一个来修复所述多个存储器列中的至少一个，并且响应于输入/输出修复模式来控制使用冗余存储器列同时修复的存储器列的数量 控制信号。

公开(公告)号：US20070133271A1

公开(公告)日：2007-06-14

申请号：US11605212

申请日：2006-11-29

申请人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

发明人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

摘要翻译： 公开了一种可变相存储器件和读取数据的相关方法。 存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元包括相位可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路通过高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。 存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

公开(公告)号：US20070103972A1

公开(公告)日：2007-05-10

申请号：US11316017

申请日：2005-12-23

申请人： Yu-Hwan Ro ,  Woo-Yeong Cho ,  Byung-Gil Choi

发明人： Yu-Hwan Ro ,  Woo-Yeong Cho ,  Byung-Gil Choi

IPC分类号： G11C11/00

CPC分类号： G11C5/145 ,  G11C5/143 ,  G11C7/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2213/72

摘要： In one aspect, a non-volatile semiconductor memory device includes a phase phase-change memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of phase-change memory cells, where each the phase-change memory cells includes a phase-change resistive element and a diode connected in series between a word line and a bit line among the plurality of word lines and bit lines of the phase-change memory cell array. The memory device of this aspect further includes a sense node which is selectively connected to a bit line of the phase-change memory cell array, a boosting circuit which generates a boosted voltage which is greater than an internal power supply voltage, a pre-charge and biasing circuit which is driven by the boosted voltage to pre-charge and bias the sense node, and a sense amplifier connected to the sense node. The boosted voltage may be equal to or greater than a sum of the internal power supply voltage and a threshold voltage of the diode of each phase-change memory cell.

摘要翻译： 一方面，一种非易失性半导体存储器件包括：相位相变存储单元阵列，包括多个字线，多个位线和多个相变存储器单元，其中每个相变存储器 单元包括在相变存储单元阵列的多个字线和位线之间串联连接在字线和位线之间的相变电阻元件和二极管。 该方面的存储装置还包括有选择地连接到相变存储单元阵列的位线的感测节点，产生大于内部电源电压的升压电压的升压电路，预充电 以及由升压电压驱动以对感测节点进行预充电和偏置的偏置电路，以及连接到感测节点的读出放大器。 升压电压可以等于或大于内部电源电压和每个相变存储单元的二极管的阈值电压之和。

公开(公告)号：US07110286B2

公开(公告)日：2006-09-19

申请号：US10919371

申请日：2004-08-17

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

公开(公告)号：US20060104102A1

公开(公告)日：2006-05-18

申请号：US11183613

申请日：2005-07-18

申请人： Byung-Gil Choi ,  Young-Ho Suh ,  Choong-Keun Kwak

发明人： Byung-Gil Choi ,  Young-Ho Suh ,  Choong-Keun Kwak

IPC分类号： G11C5/06

CPC分类号： G11C7/02 ,  G11C7/18

摘要： A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the first direction, wherein the true bit line and the complementary bit line comprising a bit line pair.

摘要翻译： 真正的位线可以沿第一方向跨越存储器件的存储器单元区域延伸，并且互补位线可以在与第一方向相反的第二方向跨越存储器单元区域延伸，其中真位线和互补位线 包括位线对。

公开(公告)号：US20060028886A1

公开(公告)日：2006-02-09

申请号：US11124341

申请日：2005-05-06

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C7/00

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A drive circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器减小了较高外围温度的宽度。

公开(公告)号：US20050162303A1

公开(公告)日：2005-07-28

申请号：US11079198

申请日：2005-03-15

申请人： Baek-Hyung Cho ,  Woo-Yeong Cho ,  Hyung-Rok Oh ,  Byung-Gil Choi

发明人： Baek-Hyung Cho ,  Woo-Yeong Cho ,  Hyung-Rok Oh ,  Byung-Gil Choi

IPC分类号： G11C13/00 ,  G11C13/02 ,  G11C16/02 ,  H01L27/105 ,  H01L45/00 ,  H03M3/00

CPC分类号： G11C13/0004 ,  G11C7/04 ,  G11C13/0069 ,  G11C2013/0078

摘要： A programming method which controls the amount of a write current applied to a Phase-change Random Access Memory (PRAM), and a write driver circuit realizing the programming method. The programming method includes maintaining a ratio of a resistance of the PCM in the higher resistance state to a resistance of the PCM in the lower resistance state constant or substantially constant independent of an ambient temperature. The ratio may be maintained by increasing, decreasing, or keeping the same a reset current and/or a set current.

摘要翻译： 控制施加到相变随机存取存储器（PRAM）的写入电流的量的编程方法以及实现编程方法的写入驱动器电路。 编程方法包括保持PCM在较高电阻状态下的电阻与PCM在较低电阻状态下的电阻的比率恒定或基本恒定，而与环境温度无关。 可以通过增加，减少或保持相同的复位电流和/或设定电流来维持该比率。

公开(公告)号：US20050007843A1

公开(公告)日：2005-01-13

申请号：US10889194

申请日：2004-07-12

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C29/812 ,  G11C29/806

摘要： A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.

摘要翻译： 一种具有多块结构的半结构存储器件中的冗余电路，其中存储单元阵列被分为多个存储单元块，集成冗余电路具有多个保险丝盒，用于存储每块所提供的不良存储器单元的地址 在所述多个存储单元块中，所述多个保险丝盒连接到所述公共预充电单元，并且响应于块区别选择信号被选择性地激活。

公开(公告)号：US08264905B2

公开(公告)日：2012-09-11

申请号：US12406441

申请日：2009-03-18

申请人： Byung-Gil Choi ,  Du-Eung Kim

发明人： Byung-Gil Choi ,  Du-Eung Kim

IPC分类号： G11C16/08

CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2029/1202

摘要： A nonvolatile memory device using variable resistive element with reduced layout size and improved performance is provided. The nonvolatile memory device comprising: a main word line; multiple sub-word lines, wherein each of the sub-word line is connected to multiple nonvolatile memory cells; and a section word line driver which controls voltage level of the multiple sub-word lines, wherein the section word line driver includes multiple pull-down elements which are connected to each of the multiple sub-word lines and a common node and a selection element which is connected to the common node and the main word line.

摘要翻译： 提供了使用可变电阻元件的非易失性存储器件，其具有减小的布局尺寸和改进的性能。 所述非易失性存储器件包括：主字线; 多个子字线，其中每个子字线连接到多个非易失性存储器单元; 以及区域字线驱动器，其控制所述多个子字线的电压电平，其中所述部分字线驱动器包括连接到所述多个子字线中的每一个的多个下拉元件，以及公共节点和选择元件 其连接到公共节点和主字线。