中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.019 seconds)

    Stacked silicon package assembly having vertical thermal management
    11.
    发明授权
    Stacked silicon package assembly having vertical thermal management 有权

    公开(公告)号：US11488936B2

    公开(公告)日：2022-11-01

    申请号：US16718868

    申请日：2019-12-18

    Applicant: Xilinx, Inc.

    Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Cheang-Whang Chang

    IPC: H01L25/065 ,  H01L23/367 ,  H01L23/04 ,  H01L23/31

    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

    Stacked silicon package assembly having thermal management
    12.
    发明授权
    Stacked silicon package assembly having thermal management 有权

    公开(公告)号：US11145566B2

    公开(公告)日：2021-10-12

    申请号：US16786447

    申请日：2020-02-10

    Applicant: XILINX, INC.

    Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Cheang-Whang Chang

    IPC: H01L23/367 ,  H01L25/065

    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die. A first conductive heat transfer structure of the plurality of electrically floating conductive heat transfer structures are part of a first conductive heat transfer path having a length in the first direction at least as long as a distance between the first and second surfaces.

    In-die transistor characterization in an IC
    13.
    发明授权
    In-die transistor characterization in an IC 有权

    公开(公告)号：US10379155B2

    公开(公告)日：2019-08-13

    申请号：US14505240

    申请日：2014-10-02

    Applicant: Xilinx, Inc

    Inventor： Ping-Chin Yeh ,  John K. Jennings ,  Rhesa Nathanael ,  Nui Chong ,  Cheang-Whang Chang ,  Daniel Y Chung

    IPC: G01R31/28 ,  G01R31/3167

    Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

    Test circuits for testing a die stack
    16.
    发明授权
    Test circuits for testing a die stack 有权

    公开(公告)号：US11054461B1

    公开(公告)日：2021-07-06

    申请号：US16351310

    申请日：2019-03-12

    Applicant: Xilinx, Inc.

    Inventor： Nui Chong ,  Amitava Majumdar ,  Cheang-Whang Chang ,  Henley Liu ,  Myongseob Kim ,  Albert Shih-Huai Lin

    IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3177 ,  H01L25/065

    Abstract: Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.

    PACKAGE INTEGRATION FOR MEMORY DEVICES
    17.
    发明申请
    PACKAGE INTEGRATION FOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200303341A1

    公开(公告)日：2020-09-24

    申请号：US16361617

    申请日：2019-03-22

    Applicant: Xilinx, Inc.

    Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

    IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

    Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.

    Package integration for memory devices
    18.
    发明授权
    Package integration for memory devices 有权

    公开(公告)号：US10770430B1

    公开(公告)日：2020-09-08

    申请号：US16361617

    申请日：2019-03-22

    Applicant: Xilinx, Inc.

    Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

    IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

    Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.

    Chip package assembly with modular core dice
    19.
    发明授权
    Chip package assembly with modular core dice 有权

    公开(公告)号：US10692837B1

    公开(公告)日：2020-06-23

    申请号：US16041530

    申请日：2018-07-20

    Applicant: Xilinx, Inc.

    Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Nui Chong

    IPC: H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

    Abstract: A chip package assembly and method for fabricating the same are provided which utilize at least one modular core dice to reduce the cost of manufacture. The modular core dice include at least two die disposed on a wafer segment that are separated by a scribe lane. In one example, a chip package assembly is provided that includes an interconnect substrate stacked below a first wafer segment. The first wafer segment has a first die spaced from a second die by a first scribe lane. The interconnect substrate has conductive routing that is electrically connected to the first die and the second die through die connections.

    Wafer edge partial die engineered for stacked die yield
    20.
    发明授权
    Wafer edge partial die engineered for stacked die yield 有权

    公开(公告)号：US10431565B1

    公开(公告)日：2019-10-01

    申请号：US15907034

    申请日：2018-02-27

    Applicant: Xilinx, Inc.

    Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang

    IPC: H01L25/065 ,  H01L23/522 ,  H01L25/00 ,  H01L23/00

    Abstract: A stacked wafer assembly and method for fabricating the same are described herein. In one example, a stacked wafer assembly includes a first wafer bonded to a second wafer. The first wafer includes a plurality of fully functional dies and a first partial die formed thereon. The second wafer includes a plurality of fully functional dies and a first partial die formed thereon. Bond pads formed over an inductor of the first partial die of the first wafer are bonded to bond pads formed on the first partial die of the second wafer to establish electrical connection therebetween.

Patent Agency Ranking