公开(公告)号：US20230069505A1

公开(公告)日：2023-03-02

申请号：US17411891

申请日：2021-08-25

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Sagheer AHMAD

IPC: G06F13/20

Abstract: Transmitter circuitry includes inversion circuitry, first transform circuitry, and selection circuitry. The inversion circuitry generates a first transformed data word by inverting one or more of a plurality of bits of a first data word. The first transform circuitry generates a second transformed data word by performing a first invertible operation on the first data word and a second data word. The selection circuitry selects one of the first data word, the first transformed data word, and the second transformed data word based on a first number of bit inversions between the first data word and the second data word, a second number of bit inversions between the first transformed data word and the second data word, and a third number of bit inversions between the second transformed data word and the second data word. The selection circuitry further outputs the selected data word.

公开(公告)号：US20240387388A1

公开(公告)日：2024-11-21

申请号：US18199334

申请日：2023-05-18

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE ,  Sagheer AHMAD ,  Aman GUPTA

IPC: H01L23/538 ,  H01L25/065 ,  H10B80/00

Abstract: Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.

公开(公告)号：US20240176758A1

公开(公告)日：2024-05-30

申请号：US18432847

申请日：2024-02-05

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0016

Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

公开(公告)号：US20240111704A1

公开(公告)日：2024-04-04

申请号：US17959903

申请日：2022-10-04

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Abbas MORSHED ,  Sagheer AHMAD

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/4022

Abstract: Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.

公开(公告)号：US20240111693A1

公开(公告)日：2024-04-04

申请号：US17957418

申请日：2022-09-30

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD ,  Sarosh I. AZAD ,  Pramod BHARDWAJ ,  Yanran CHEN ,  James MURRAY

IPC: G06F13/16 ,  G06F11/07

CPC classification number: G06F13/1631 ,  G06F11/0772 ,  G06F13/1668

Abstract: Techniques to provide transaction redundancy in an IC include receiving an original memory access request directed to a first memory aperture, constructing a redundant memory access directed to a second memory aperture, and selectively returning a response of the first or second memory aperture to an originator based on contents of the responses. For a write operation, if acknowledgement indicators of the responses indicate success, a response is returned to the originator. For a read operation, if acknowledgement indicators of the responses indicate success and data returned in the response match one another, a response is returned to the originator. If the acknowledgement indicators indicate success, but the data does not match, a retry of the original and redundant read requests is initiated. If any of the acknowledgement indicators do not indicate success, an error is declared. In a mixed-criticality embodiment, the redundant memory access request may be constructed selectively.

公开(公告)号：US20230244628A1

公开(公告)日：2023-08-03

申请号：US17589633

申请日：2022-01-31

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Sagheer AHMAD ,  Ygal ARBEL ,  Millind MITTAL

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/42 ,  G06F13/382 ,  G06F13/4063

Abstract: Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.

公开(公告)号：US20250167152A1

公开(公告)日：2025-05-22

申请号：US19032979

申请日：2025-01-21

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Kenneth MA ,  Balakrishna JAYADEV ,  Sagheer AHMAD

IPC: H01L23/00 ,  G11C5/06 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

公开(公告)号：US20240411715A1

公开(公告)日：2024-12-12

申请号：US18807703

申请日：2024-08-16

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Sagheer AHMAD ,  Ygal ARBEL ,  Millind MITTAL

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40

Abstract: Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.

公开(公告)号：US20240211422A1

公开(公告)日：2024-06-27

申请号：US18086531

申请日：2022-12-21

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  Krishnan SRINIVASAN ,  Ahmad R. ANSARI ,  Sagheer AHMAD

IPC: G06F13/40 ,  G06F12/1009

CPC classification number: G06F13/4022 ,  G06F12/1009 ,  G06F13/4036 ,  G06F13/4068 ,  G06F2213/0038

Abstract: Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.

公开(公告)号：US20240045822A1

公开(公告)日：2024-02-08

申请号：US17879675

申请日：2022-08-02

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD ,  Abbas MORSHED

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F2213/40

Abstract: Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.