公开(公告)号：US06229685B1

公开(公告)日：2001-05-08

申请号：US09467734

申请日：1999-12-20

Applicant: Subhas Bothra ,  Dipankar Pramanik ,  Calvin T. Gabriel

Inventor： Subhas Bothra ,  Dipankar Pramanik ,  Calvin T. Gabriel

IPC: H01G4228

CPC classification number: H01L28/60 ,  H01L28/55

Abstract: A capacitor and a method of making the capacitor is provided. The capacitor includes a metallization line with a high dielectric constant layer defined over the metallization line. A thin metallization film is defined over the high dielectric constant layer, such that the thin metallization film defines a top plate of the capacitor, the high dielectric constant layer defines a dielectric for the capacitor, and the metallization line defines a bottom plate for the capacitor. The metallization line is defined from a metallization level and the thin metallization film is defined before a next metallization level above the metallization level is defined.

Abstract translation: 提供电容器和制造电容器的方法。 电容器包括金属化线，其具有限定在金属化线上的高介电常数层。 在高介电常数层上限定薄金属化膜，使得薄金属化膜限定电容器的顶板，高介电常数层限定用于电容器的电介质，并且金属化线限定用于电容器的底板 。 金属化线由金属化水平限定，并且在限定金属化水平以上的下一个金属化水平之前限定薄金属化膜。

公开(公告)号：US06221759B1

公开(公告)日：2001-04-24

申请号：US09100639

申请日：1998-06-19

Applicant: Subhas Bothra ,  Stephen L. Skala

Inventor： Subhas Bothra ,  Stephen L. Skala

IPC: H01L214763

CPC classification number: H01L21/76807

Abstract: Disclosed is a method for forming an aligned via under a trench to prevent voiding in a dual damascene process. The trench is formed in an oxide layer that is formed over a first metal layer and the first metal layer is formed over a semiconductor substrate. The method includes forming an etch stop layer over the oxide layer and forming a set of adjacent trenches in the oxide layer through a portion of the etch stop layer. The method also includes forming a resist layer at least partially over the etch stop layer. The resist layer is formed in a via pattern to expose the set of adjacent trenches through the via pattern. The method further includes etching the oxide layer under the set of adjacent trenches until the oxide layer is etched through to expose at least a portion of the first metal layer so as to form a via under each of the adjacent trenches. In this process, the etch stop layer inhibits the oxide layer underneath from being etched substantially such that each of the vias formed under the each of the adjacent trenches is substantially of a same width as and in alignment with the associated trench above.

Abstract translation: 公开了一种用于在沟槽下形成对准的通孔以防止双镶嵌工艺中的空隙的方法。 沟槽形成在形成在第一金属层上的氧化物层中，并且第一金属层形成在半导体衬底上。 该方法包括在氧化物层上形成蚀刻停止层，并通过蚀刻停止层的一部分在氧化物层中形成一组相邻的沟槽。 该方法还包括至少部分地在蚀刻停止层上形成抗蚀剂层。 抗蚀剂层形成为通孔图案，以通过通孔图案露出该组相邻的沟槽。 该方法还包括蚀刻相邻沟槽组之下的氧化物层，直到蚀刻氧化层以露出第一金属层的至少一部分，以便在每个相邻的沟槽下形成通孔。 在该过程中，蚀刻停止层抑制下面的氧化物层被基本蚀刻，使得形成在每个相邻沟槽之下的每个通孔基本上具有与上述相关沟槽相同的宽度和与之相对应的沟槽的对准。

公开(公告)号：US6010939A

公开(公告)日：2000-01-04

申请号：US052865

申请日：1998-03-31

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/20

CPC classification number: H01L21/76224 ,  H01L21/763

Abstract: Disclosed is a capacitive structure and method for making the capacitive structure for suppressing inductive noise produced by high performance device power supplies. The capacitive structure includes a trench having a bottom surface and respective walls that are integral with the bottom surface. The trench is defined in a semiconductor substrate and is configured to isolate at least one transistor active area from another transistor active area. The structure further includes an oxide layer that is defined along the bottom surface and the respective walls of the trench, such that a channel is defined within the trench between the oxide layer that is defined along the bottom surface and the respective walls. The structure also includes a conductive polysilicon layer that is defined within the channel and is within the trench. The conductive polysilicon layer defines a conductive electrode that is separated from the semiconductor substrate by a thickness of the oxide layer.

Abstract translation: 公开了用于制造用于抑制由高性能器件电源产生的感应噪声的电容结构的电容结构和方法。 电容结构包括具有底表面和与底表面成一体的相应壁的沟槽。 沟槽被限定在半导体衬底中并且被配置为将至少一个晶体管有源区与另一晶体管有源区隔离。 该结构还包括沿着沟槽的底表面和相应壁限定的氧化物层，使得在沿着底表面限定的氧化物层和相应壁之间的沟槽内限定沟道。 该结构还包括限定在沟道内并且在沟槽内的导电多晶硅层。 导电多晶硅层限定了通过氧化物层的厚度与半导体衬底分离的导电电极。

公开(公告)号：US5976987A

公开(公告)日：1999-11-02

申请号：US943839

申请日：1997-10-03

Applicant: Ian Robert Harvey ,  Calvin Todd Gabriel ,  Subhas Bothra

Inventor： Ian Robert Harvey ,  Calvin Todd Gabriel ,  Subhas Bothra

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/76804 ,  H01L21/31116

Abstract: A self-aligned contact etch and method for forming a self-aligned contact etch. In one embodiment, the present invention performs an oxide selective etch to form an opening originating at a top surface of a photoresist layer. The opening extends through an underlying oxide layer, and terminates at a top surface of a nitride layer which underlies the oxide layer. Next, the present invention performs a nitride selective etch to extend the opening through the nitride layer to an underlying contact layer. In the present invention, the nitride selective etch causes the photoresist layer to be etched/receded. The nitride selective etch of the present invention further causes the oxide layer to be etched at and near the opening at the interface between the photoresist layer and the oxide layer. As a result, the opening is rounded at the top edge thereof when the layer of photoresist is removed.

Abstract translation: 用于形成自对准接触蚀刻的自对准接触蚀刻和方法。 在一个实施方案中，本发明进行氧化物选择性蚀刻以形成源于光致抗蚀剂层的顶表面的开口。 开口延伸通过下面的氧化物层，并且终止于在氧化物层下面的氮化物层的顶表面。 接下来，本发明进行氮化物选择性蚀刻以将穿过氮化物层的开口延伸到下面的接触层。 在本发明中，氮化物选择性蚀刻使光致抗蚀剂层被蚀刻/后退。 本发明的氮化物选择性蚀刻还使得在光致抗蚀剂层和氧化物层之间的界面处的开口处和附近蚀刻氧化物层。 结果，当去除光致抗蚀剂层时，开口在其顶部边缘处是圆形的。

公开(公告)号：US5913141A

公开(公告)日：1999-06-15

申请号：US134741

申请日：1998-08-14

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76876 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/927

Abstract: Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying the first patterned metallization layer and the first dielectric layer. An aluminum filled via hole defined through the second dielectric layer and in contact with the first patterned metallization layer. The aluminum filled via hole has an electromigration barrier cap over a topmost portion of the aluminum filled via hole that is substantially level with the second dielectric layer. The electromigration barrier cap having a thickness of between about 500 angstroms and about 2,500 angstroms.

公开(公告)号：US5764563A

公开(公告)日：1998-06-09

申请号：US723007

申请日：1996-09-30

Applicant: Harlan Lee Sur, Jr. ,  Subhas Bothra

Inventor： Harlan Lee Sur, Jr. ,  Subhas Bothra

IPC: G11C11/412 ,  H01L21/02 ,  H01L27/11 ,  G11C11/00

CPC classification number: H01L28/20 ,  G11C11/412 ,  H01L27/1112

Abstract: A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.

Abstract translation: 用于制造用于集成电路的电阻负载结构的电阻负载结构和方法包括使用非晶硅“反熔丝”材料。 电阻负载结构可用于SRAM单元中，以提供负载以抵消SRAM单元的两个下拉晶体管和两个通过晶体管的漏极处的电荷泄漏。 有利地通过在导电通孔上沉积非晶硅垫来形成电阻负载结构，并且通过调节非晶硅垫的厚度并改变下面的导电通孔的直径来控制电阻负载结构的电阻。

公开(公告)号：US20070083833A1

公开(公告)日：2007-04-12

申请号：US11244514

申请日：2005-10-06

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

Abstract: Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout. Additionally, because the physical characteristics of inactive metal fill segments are considered during design and layout of the ICs.

Abstract translation: 本发明的实施例提供了一种系统和方法，用于在设计期间使用诸如位置和路线工具或布局工具的工具来实现金属填充。 与在设计和布局之后执行金属填充的现有已知解决方案不同，在布局期间，根据要制造的器件的设计规则，均匀地形成导电迹线图案并进行间隔，从而实现更多的规划和设计，进行金属填充。 在设计和布局期间，将导电迹线划分为有源和无源段可以在设计和布局期间识别器件内的关键或敏感器件元件的潜在负面影响。 以前，设计和布局后实施了金属填充，并且经常导致IC设计中以前未考虑的负面影响。 本发明的实施例减少了在设计和布局之后掺入金属填充物的其他装置中的劣化。 另外，因为在IC的设计和布局期间考虑了非活性金属填充段的物理特性。

公开(公告)号：US06717232B2

公开(公告)日：2004-04-06

申请号：US10406914

申请日：2003-04-02

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L2900

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F41/042 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor inductor and a method for making a semiconductor inductor are provided. An oxide layer disposed over a substrate is etched to form an interconnect metallization trench within the oxide layer. The oxide layer is also etched to form a first inductor trench within the oxide layer such that the first inductor trench is defined in an inductor geometry. The oxide layer is then etched to form at least one via in the interconnect metallization trench and a second inductor trench over the first inductor trench in the oxide layer. The second inductor trench also has the inductor geometry. After the oxide layer is etched, the at least one via, the second inductor trench, the interconnect metallization trench and the first inductor trench are filled with copper. The semiconductor inductor is configured to have a low resistance and a high quality factor.

Abstract translation: 提供半导体电感器和制造半导体电感器的方法。 蚀刻设置在衬底上的氧化物层以在氧化物层内形成互连金属化沟槽。 也蚀刻氧化物层以在氧化物层内形成第一电感器沟槽，使得第一电感器沟槽以电感器几何形状限定。 然后蚀刻氧化物层以在互连金属化沟槽中形成至少一个通孔，以及在氧化物层中的第一电感器沟槽上方的第二电感器沟槽。 第二电感沟槽也具有电感器几何形状。 在蚀刻氧化物层之后，铜填充至少一个通孔，第二电感器沟槽，互连金属化沟槽和第一电感器沟槽。 半导体电感器被配置为具有低电阻和高品质因数。

公开(公告)号：US06649253B1

公开(公告)日：2003-11-18

申请号：US09523403

申请日：2000-03-10

Applicant: Subhas Bothra ,  Milind G. Weling

Inventor： Subhas Bothra ,  Milind G. Weling

IPC: H01L2500

CPC classification number: B24B37/013 ,  B24B37/042 ,  H01L21/31053 ,  Y10S438/959 ,  Y10T428/24917

Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer. Furthermore, the present invention enables the operator of the CMP machine to know within a certain accuracy the film (e.g., dielectric layer) thickness remaining after the CMP process of the semiconductor wafer. Moreover, the present invention essentially eliminates excessive chemical mechanical polishing of the semiconductor wafer. As such, not as much dielectric material needs to be deposited on the wafer in order to compensate for excessive chemical mechanical polishing of the semiconductor wafer. Therefore, the present invention is able to reduce fabrication costs of semiconductor wafers.

Abstract translation: 使用具有优化的光学性质的膜用于化学机械抛光（CMP）端点检测的方法。 具体地，本发明的一个实施方案包括用于改进化学机械抛光终点检测的方法。 该方法包括在反射停止层上沉积介电层的步骤。 反射阻挡层设置在配置在半导体晶片上的部件的上方。 在使用光的反射信号确定介电层的厚度期间，反射率停止层基本上减少了从组件反射的任何光。 因此，本发明提供了一种在半导体晶片的CMP工艺期间提供更准确的端点检测的方法和系统。 作为本发明的结果，CMP机器的操作者精确地知道何时停止半导体晶片的CMP工艺。 此外，本发明使得CMP机器的操作者能够在半导体晶片的CMP处理之后以一定的精度了解剩余的膜（例如介电层）的厚度。 此外，本发明基本上消除了半导体晶片的过度的化学机械抛光。 因此，为了补偿半导体晶片的过度的化学机械抛光，不需要在晶片上沉积太多的介电材料。 因此，本发明能够降低半导体晶片的制造成本。

公开(公告)号：US06569757B1

公开(公告)日：2003-05-27

申请号：US09429540

申请日：1999-10-28

Applicant: Milind Weling ,  Subhas Bothra ,  Calvin Todd Gabriel ,  Michael Misheloff

Inventor： Milind Weling ,  Subhas Bothra ,  Calvin Todd Gabriel ,  Michael Misheloff

IPC: H01L214763

CPC classification number: H01L23/5225 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  Y10T29/49123 ,  H01L2924/00

Abstract: A method of forming a co-axial interconnect line in a dielectric layer is provided. The method includes defining a trench in the dielectric layer and then forming a shield metallization layer within the trench. After forming the shield metallization layer, a conformal oxide layer is deposited within the shield metallization layer. A center conductor is then formed within the conformal oxide layer. Once the center conductor is formed, a fill oxide layer is deposited over the center conductor. A cap metallization layer is then formed over the fill oxide layer and is in contact with the shield metallization layer.

Abstract translation: 提供了在电介质层中形成同轴互连线的方法。 该方法包括在电介质层中限定沟槽，然后在沟槽内形成屏蔽金属化层。 在形成屏蔽金属化层之后，在屏蔽金属化层内沉积保形氧化物层。 然后在保形氧化物层内形成中心导体。 一旦形成中心导体，就在中心导体上沉积填充氧化物层。 然后在填充氧化物层上形成帽金属化层，并与屏蔽金属化层接触。