公开(公告)号：US10103139B2

公开(公告)日：2018-10-16

申请号：US14792847

申请日：2015-07-07

Applicant: Xilinx, Inc.

Inventor： Nui Chong ,  Jae-Gyung Ahn ,  Ping-Chin Yeh ,  Cheang-Whang Chang

IPC: H01L29/00 ,  H01L23/62 ,  H01L27/07 ,  H01L23/522 ,  H01L27/06 ,  H01L49/02 ,  H01L21/283 ,  H01L21/76 ,  H01L27/02

Abstract: An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the STI region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.

公开(公告)号：US11164749B1

公开(公告)日：2021-11-02

申请号：US16571766

申请日：2019-09-16

Applicant: XILINX, INC.

Inventor： Nui Chong ,  Hui-Wen Lin

IPC: H01L21/302 ,  H01L23/498 ,  H01L21/67 ,  H01L23/00 ,  H01L29/78

Abstract: Examples described herein provide a method for reducing warpage when stacking semiconductor substrates. In an example, a first substrate is bonded with a second substrate to form a stack. The first substrate comprises a first semiconductor substrate, and the second substrate comprises a second semiconductor substrate. The second semiconductor substrate is thinned, and a first trench is etched into a backside of the thinned second semiconductor substrate. A first stressed material is deposited into the first trench.

公开(公告)号：US11114344B1

公开(公告)日：2021-09-07

申请号：US16805398

申请日：2020-02-28

Applicant: XILINX, INC.

Inventor： Hui-Wen Lin ,  Nui Chong ,  Myongseob Kim ,  Henley Liu ,  Ping-Chin Yeh ,  Cheang-whang Chang

IPC: H01L21/82 ,  H01L23/50 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105

Abstract: Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is formed in the buffer zone and is also at least partially fabricated from the gate metal layer. An amount of gate metal layer material in the dummy structure is selected to mitigate differences in the amount of gate metal layer material in regions of first and second circuit blocks that neighbor each other across the buffer zone.

公开(公告)号：US10379155B2

公开(公告)日：2019-08-13

申请号：US14505240

申请日：2014-10-02

Applicant: Xilinx, Inc

Inventor： Ping-Chin Yeh ,  John K. Jennings ,  Rhesa Nathanael ,  Nui Chong ,  Cheang-Whang Chang ,  Daniel Y Chung

IPC: G01R31/28 ,  G01R31/3167

Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

公开(公告)号：US20200006186A1

公开(公告)日：2020-01-02

申请号：US16024670

申请日：2018-06-29

Applicant: Xilinx, Inc.

Inventor： Hong-Tsz Pan ,  Jonathan Chang ,  Nui Chong ,  Henley Liu ,  Gamal Refai-Ahmed ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/528

Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.

公开(公告)号：US20170012041A1

公开(公告)日：2017-01-12

申请号：US14792847

申请日：2015-07-07

Applicant: Xilinx, Inc.

Inventor： Nui Chong ,  Jae-Gyung Ahn ,  Ping-Chin Yeh ,  Cheang-Whang Chang

IPC: H01L27/07 ,  H01L21/76 ,  H01L21/283 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L27/0738 ,  H01L21/283 ,  H01L21/76 ,  H01L23/5228 ,  H01L27/0207 ,  H01L27/0629 ,  H01L28/24

Abstract: An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the STI region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.

Abstract translation: 集成电路结构包括：半导体衬底; 在半导体衬底中的浅沟槽隔离（STI）区域; 形成在半导体衬底上的一个或多个有源器件; 以及具有设置在所述STI区域上方的多个电阻器的电阻器阵列; 其中所述电阻器阵列包括用于与所述一个或多个有源器件互连的一个或多个互连接触层的一部分。

公开(公告)号：US09177634B1

公开(公告)日：2015-11-03

申请号：US14172835

申请日：2014-02-04

Applicant: Xilinx, Inc.

Inventor： Steven P. Young ,  Yang Song ,  Nui Chong

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/41 ,  H03K19/177

CPC classification number: H01L27/0207 ,  G11C11/41 ,  H01L27/1104 ,  H01L27/11807 ,  H03K19/177 ,  H03K19/1776

Abstract: A memory cell includes a first inverter and a second inverter, wherein the first inverter and second inverter are cross-coupled using a storage node and an inverse storage node; a data node and an inverse data node, wherein the data node and inverse data node are next to a first side of the memory cell; and an address line controlling access to the storage node and the inverse storage node by the data and inverse data nodes; wherein the memory cell comprises a two gate pitch memory cell.

Abstract translation: 存储单元包括第一反相器和第二反相器，其中第一反相器和第二反相器使用存储节点和反向存储节点进行交叉耦合; 数据节点和逆数据节点，其中所述数据节点和逆数据节点在所述存储器单元的第一侧旁边; 以及地址线，其通过数据和逆数据节点控制对存储节点和逆存储节点的访问; 其中所述存储单元包括两个门间距存储单元。