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    METHOD AND DESIGN OF LOW SHEET RESISTANCE MEOL RESISTORS
    1.
    发明申请
    METHOD AND DESIGN OF LOW SHEET RESISTANCE MEOL RESISTORS 审中-公开
    低电阻电阻器的方法和设计

    公开(公告)号：US20170012041A1

    公开(公告)日：2017-01-12

    申请号：US14792847

    申请日：2015-07-07

    Applicant: Xilinx, Inc.

    Inventor： Nui Chong ,  Jae-Gyung Ahn ,  Ping-Chin Yeh ,  Cheang-Whang Chang

    IPC: H01L27/07 ,  H01L21/76 ,  H01L21/283 ,  H01L49/02 ,  H01L27/02

    CPC classification number: H01L27/0738 ,  H01L21/283 ,  H01L21/76 ,  H01L23/5228 ,  H01L27/0207 ,  H01L27/0629 ,  H01L28/24

    Abstract: An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the STI region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.

    Abstract translation: 集成电路结构包括：半导体衬底; 在半导体衬底中的浅沟槽隔离（STI）区域; 形成在半导体衬底上的一个或多个有源器件; 以及具有设置在所述STI区域上方的多个电阻器的电阻器阵列; 其中所述电阻器阵列包括用于与所述一个或多个有源器件互连的一个或多个互连接触层的一部分。

    IC die with dummy structures
    2.
    发明授权
    IC die with dummy structures 有权

    公开(公告)号：US11114344B1

    公开(公告)日：2021-09-07

    申请号：US16805398

    申请日：2020-02-28

    Applicant: XILINX, INC.

    Inventor： Hui-Wen Lin ,  Nui Chong ,  Myongseob Kim ,  Henley Liu ,  Ping-Chin Yeh ,  Cheang-whang Chang

    IPC: H01L21/82 ,  H01L23/50 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105

    Abstract: Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is formed in the buffer zone and is also at least partially fabricated from the gate metal layer. An amount of gate metal layer material in the dummy structure is selected to mitigate differences in the amount of gate metal layer material in regions of first and second circuit blocks that neighbor each other across the buffer zone.

    In-die transistor characterization in an IC
    3.
    发明授权
    In-die transistor characterization in an IC 有权

    公开(公告)号：US10379155B2

    公开(公告)日：2019-08-13

    申请号：US14505240

    申请日：2014-10-02

    Applicant: Xilinx, Inc

    Inventor： Ping-Chin Yeh ,  John K. Jennings ,  Rhesa Nathanael ,  Nui Chong ,  Cheang-Whang Chang ,  Daniel Y Chung

    IPC: G01R31/28 ,  G01R31/3167

    Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

    IN-DIE TRANSISTOR CHARACTERIZATION IN AN IC
    4.
    发明申请
    IN-DIE TRANSISTOR CHARACTERIZATION IN AN IC 审中-公开
    IC中的In-DIE晶体管特性

    公开(公告)号：US20160097805A1

    公开(公告)日：2016-04-07

    申请号：US14505240

    申请日：2014-10-02

    Applicant: Xilinx, Inc

    Inventor： Ping-Chin Yeh ,  John K. Jennings ,  Rhesa Nathanael ,  Nui Chong ,  Cheang-Whang Chang ,  Daniel Y. Chung

    IPC: G01R31/28

    CPC classification number: G01R31/2851 ,  G01R31/2837 ,  G01R31/2843 ,  G01R31/3167

    Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

    Abstract translation: 在示例实现中，集成电路（IC）包括：设置在IC的管芯上的多个位置中的多个晶体管; 耦合到所述多个晶体管中的每一个的端子的导体; 耦合到所述导体的数模转换器（DAC），以响应于数字输入将电压信号驱动到所述多个晶体管; 以及耦合到所述导体的至少一部分的模数转换器（ADC），以响应于所述电压信号而响应于在所述多个晶体管中感应的电流信号而生成样本，所述样本至少指示 一个静电特性用于多个晶体管。

    Implantation for etch stop liner
    6.
    发明授权
    Implantation for etch stop liner 有权

    公开(公告)号：US11107696B1

    公开(公告)日：2021-08-31

    申请号：US16667176

    申请日：2019-10-29

    Applicant: XILINX, INC.

    Inventor： Li-Wen Chang ,  Ping-Chin Yeh

    IPC: H01L21/336 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/265 ,  H01L21/311 ,  H01L21/768

    Abstract: Examples described herein provide for methods for semiconductor processing for forming source/drain regions of transistors. An example is a method for semiconductor processing. An etch stop liner is formed in a semiconductor substrate. Forming the etch stop liner includes implanting etch selectivity dopants into the semiconductor substrate. The etch selectivity dopants form at least part of the etch stop liner. A source/drain cavity is formed in the semiconductor substrate. Forming the source/drain cavity includes etching the etch stop liner. Etching the etch stop liner selectively etches the etch stop liner relative to a material of the semiconductor substrate. A source/drain region is epitaxially grown in the source/drain cavity.

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