公开(公告)号：US08769477B1

公开(公告)日：2014-07-01

申请号：US13756339

申请日：2013-01-31

Applicant: Xilinx, Inc.

Inventor： Yogesh Gathoo ,  Siddharth Rele ,  Gregory A. Brown ,  Avdhesh Palliwal ,  Gangadhar Budde ,  Sumit Nagpal

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A user interface for a computer-aided design tool includes a display. The display includes a visualization of a processor system of a system-on-a-chip (SOC). The visualization includes a plurality of blocks and each block represents a component of the processor system. Each block visually indicates a configuration status of the component represented by the block.

Abstract translation: 用于计算机辅助设计工具的用户界面包括显示器。 显示器包括片上系统（SOC）的处理器系统的可视化。 可视化包括多个块，并且每个块表示处理器系统的组件。 每个块可视地指示由块表示的组件的配置状态。

公开(公告)号：US11188684B2

公开(公告)日：2021-11-30

申请号：US16686070

申请日：2019-11-15

Applicant: XILINX, INC.

Inventor： Gangadhar Budde ,  Shreegopal S. Agrawal ,  Siddharth Rele ,  Subhojit Deb

IPC: G06F21/76

Abstract: Creation of subsystems for a user design to be implemented in an integrated circuit (IC) includes generating, using computer hardware, a subsystem topology based on user provided subsystem data, wherein the subsystem topology specifies a plurality of subsystems of the user design where each subsystem includes a master circuit, and determining, using the computer hardware, a system management identifier for each master circuit of the subsystem topology. Programming data for programmable protection circuits of the IC can be automatically generated using the computer hardware based on the subsystem topology and system management identifiers. The programmable protection circuits, when programmed with the programming data, form the plurality of subsystems and physically isolate the plurality of subsystems on the integrated circuit from one another.

公开(公告)号：US20190324806A1

公开(公告)日：2019-10-24

申请号：US15956480

申请日：2018-04-18

Applicant: Xilinx, Inc.

Inventor： Somdutt Javre ,  Siddharth Rele ,  Gangadhar Budde ,  Appa Rao Nali ,  Chaitanya Kamarapu

IPC: G06F9/50 ,  G06F8/20 ,  G06F9/4401 ,  G06F8/30

Abstract: Multi-domain creation and isolation within a heterogeneous System-on-Chip (SoC) may include receiving a hardware description file specifying a plurality of processors and a plurality of hardware resources available within a heterogeneous SoC and creating, using computer hardware, a plurality of domains for the heterogeneous SoC, wherein each domain includes a processor selected from the plurality of processors and a hardware resource selected from the plurality of hardware resources. The method may include assigning, using the computer hardware, an operating system to each domain and generating, using the computer hardware, a platform that is configured to implement the plurality of domains within the heterogeneous SoC.

公开(公告)号：US10161999B1

公开(公告)日：2018-12-25

申请号：US15091376

申请日：2016-04-05

Applicant: Xilinx, Inc.

Inventor： Heera Nand ,  Niloy Roy ,  Mahesh Sankroj ,  Siddharth Rele ,  Riyas Noorudeen Remla ,  Rajesh Bansal ,  Bradley K. Fross

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.

公开(公告)号：US09710582B1

公开(公告)日：2017-07-18

申请号：US14974217

申请日：2015-12-18

Applicant: Xilinx, Inc.

Inventor： Sumit Nagpal ,  Siddharth Rele ,  Avdhesh Palliwal

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/66 ,  G06F2217/68

Abstract: Implementing a circuit design may include, responsive to a user input selecting a design, executing an implementation script of the design using the processor. Executing the implementation script may generate instructions for generating a circuit design from the design. Responsive to the instructions and using the processor, cores of the design may be automatically instantiated and connected.

公开(公告)号：US09465903B1

公开(公告)日：2016-10-11

申请号：US14546684

申请日：2014-11-18

Applicant: Xilinx, Inc.

Inventor： Suman Kumar Timmireddy ,  Heera Nand ,  Awdhesh Kumar Sahu ,  Brendan M. O'Higgins ,  David A. Knol ,  Siddharth Rele

IPC: G06F17/50 ,  G06F19/00 ,  H03K19/177 ,  G06F21/12 ,  G06F15/78

CPC classification number: G06F17/5054 ,  G06F15/7867 ,  G06F17/50 ,  G06F17/5022 ,  G06F21/125 ,  H03K19/17728 ,  H03K19/17748

Abstract: A method of implementing a circuit design in a circuit design tool for configuration in a programmable integrated circuit (IC) connected to components on a circuit board is described. The method includes processing a first file associated with the circuit board to obtain descriptions of circuit board interfaces of the components on the circuit board; displaying a graphic user interface (GUI) of the circuit design tool to connect a circuit board interface described in the first file with a circuit design interface in the circuit design; generating physical constraints on the circuit design interface with respect to input/outputs of the programmable IC described as being connected to the selected circuit board interface; and generating a bitstream to configure the programmable IC. The bitstream includes a physical implementation of the circuit design satisfying the physical constraints.

Abstract translation: 描述了在用于配置在与电路板上的部件连接的可编程集成电路（IC）中的电路设计工具中实现电路设计的方法。 该方法包括处理与电路板相关联的第一文件以获得电路板上组件的电路板接口的描述; 显示所述电路设计工具的图形用户界面（GUI），以将所述第一文件中描述的电路板接口与所述电路设计中的电路设计接口连接; 相对于被描述为连接到所选择的电路板接口的可编程IC的输入/输出，在电路设计接口上产生物理约束; 以及生成比特流以配置可编程IC。 比特流包括满足物理约束的电路设计的物理实现。

公开(公告)号：US08938704B1

公开(公告)日：2015-01-20

申请号：US14444693

申请日：2014-07-28

Applicant: Xilinx, Inc.

Inventor： Siddharth Rele ,  David A. Knol ,  Sumit Nagpal ,  Avdhesh Palliwal ,  Brendan M. O'Higgins

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5081

Abstract: An exemplary method of implementing a circuit design for a programmable integrated circuit (IC) includes, on at least one programmed processor, performing operations including: generating a description of circuit components of the circuit design including first portion of a circuit module that is independent of assignment of resources of the programmable IC; assigning a plurality of the resources of the programmable IC to a plurality of the circuit components including determining at least one resource assignment for the circuit module; and generating a physical implementation of the circuit components for implementation in the programmable IC, including generating a second portion of the circuit module that is dependent on the at least one resource assignment, and combining the second portion of the circuit module with the first portion of the circuit module.

Abstract translation: 实现可编程集成电路（IC）的电路设计的示例性方法包括在至少一个编程的处理器上执行操作，包括：产生电路设计的电路部件的描述，该电路设计包括电路模块的独立于 可编程IC资源的分配; 将多个可编程IC的资源分配给多个电路组件，包括确定电路模块的至少一个资源分配; 以及生成用于在可编程IC中实现的电路部件的物理实现，包括生成依赖于至少一个资源分配的电路模块的第二部分，以及将电路模块的第二部分与 电路模块。