公开(公告)号：US06407959B2

公开(公告)日：2002-06-18

申请号：US09874116

申请日：2001-06-06

申请人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

发明人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

IPC分类号： G11C700

CPC分类号： G11C16/30 ,  G11C5/14 ,  G11C5/145

摘要： A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

摘要翻译： 微型计算机包括闪存，其在相对较宽的外部电源电压范围内以稳定的方式被电擦除和编程，包括用于低电压操作的外部电源电压。 该微型计算机包括一个包括一个参考电压产生电路和一个恒压发生电路的电压钳位单元。 在操作中，电压钳位单元产生对电源电压的低依赖性的电压，并将所产生的电压钳位到在可容忍范围内低于外部单个电源电压的电压电平。 这可防止由钳位电压工作的升压电路（即编程和擦除电压）由外部提供的电压而提升的电压。

公开(公告)号：US6154412A

公开(公告)日：2000-11-28

申请号：US397851

申请日：1999-09-17

申请人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

发明人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

IPC分类号： G11C5/14 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C5/14 ,  G11C5/145

摘要： A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

摘要翻译： 一种微型计算机，包括闪存，其在相对较宽范围的外部电源电压（包括用于低电压操作的电源电压）内以稳定的方式电气地编程。微计算机包括电压钳位单元，其包括参考电压产生电路和恒定电压 发电电路。 在操作中，电压钳位单元产生对电源电压的低依赖性的电压，并将所产生的电压钳位到在可容许范围内低于外部单个电源电压的电压电平。这防止了升压电路升压的电压 在钳位电压（即编程和擦除电压）上操作，取决于外部提供的电压。

公开(公告)号：US5554489A

公开(公告)日：1996-09-10

申请号：US353256

申请日：1994-12-02

申请人： Takeo Ishibashi ,  Eiichi Ishikawa ,  Itaru Kanai

发明人： Takeo Ishibashi ,  Eiichi Ishikawa ,  Itaru Kanai

IPC分类号： G03F7/26 ,  G03F7/09 ,  H01L21/027 ,  H01L21/30 ,  G03K5/00

CPC分类号： G03F7/091 ,  H01L21/0276 ,  Y10S430/151

摘要： A forming method of a fine resist pattern improve so as to form a fine pattern of high accuracy can be obtained. A positive-type photoresist 1 including naphthoquinone diazide and novolak resin is applied on a substrate. An anti-reflection film adjusted to alkalinity is applied on positive-type photoresist 1. Positive-type photoresist 1 on which anti-reflection film 9 is applied is selectively irradiated. Positive-type photoresist 1 is developed.

摘要翻译： 可以提高精细抗蚀剂图案的形成方法，从而形成高精度的精细图案。 将包含萘醌二叠氮化物和酚醛清漆树脂的正型光致抗蚀剂1涂布在基材上。 在正性光致抗蚀剂1上涂布调整为碱度的防反射膜。选择性地照射涂有防反射膜9的正型光致抗蚀剂1。 显影正型光致抗蚀剂1。

公开(公告)号：US5539231A

公开(公告)日：1996-07-23

申请号：US397341

申请日：1995-03-02

申请人： Toshifumi Suganaga ,  Eiichi Ishikawa

发明人： Toshifumi Suganaga ,  Eiichi Ishikawa

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108 ,  H01L27/148 ,  H01L29/768

CPC分类号： H01L27/10852 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76897 ,  H01L23/53271 ,  H01L28/40 ,  H01L2924/0002

摘要： A first conductive layer and a second conductive layer are formed apart from each other on a surface of a semiconductor substrate. A first contact hole for exposing a surface of first conductive layer is formed in an interlayer insulating film. A first interconnection layer is buried in first contact hole so as to be in contact with first conductive layer. The position of the surface of first interconnection layer is the same as or lower than the surface of interlayer insulating film. The surface of first interconnection layer is covered with an insulating film. A second contact hole for exposing a surface of second conductive layer is provided in interlayer insulating film. A second conductive layer is connected to second conductive layer through second contact hole.

摘要翻译： 第一导电层和第二导电层在半导体衬底的表面上彼此分开形成。 用于暴露第一导电层的表面的第一接触孔形成在层间绝缘膜中。 第一互连层埋在第一接触孔中以与第一导电层接触。 第一互连层的表面的位置与层间绝缘膜的表面相同或更低。 第一互连层的表面被绝缘膜覆盖。 用于暴露第二导电层的表面的第二接触孔设置在层间绝缘膜中。 第二导电层通过第二接触孔连接到第二导电层。

公开(公告)号：US08171662B2

公开(公告)日：2012-05-08

申请号：US12578740

申请日：2009-10-14

申请人： Takahiro Itoh ,  Katsuaki Ohnishi ,  Hideaki Takeuchi ,  Shinji Otani ,  Shigeru Nishiyama ,  Tsutomu Ashikari ,  Eiichi Ishikawa

发明人： Takahiro Itoh ,  Katsuaki Ohnishi ,  Hideaki Takeuchi ,  Shinji Otani ,  Shigeru Nishiyama ,  Tsutomu Ashikari ,  Eiichi Ishikawa

IPC分类号： G09F3/10

CPC分类号： B26D3/085 ,  B26F3/002 ,  G09F3/0292 ,  Y10T83/0605

摘要： A method for processing a separation and rupture portion of a display label is a method for forming, on the display label attached to an attachment target object, the separation and rupture portion for rupturing the display label upon separation of the display label from the attachment target object. This method includes attaching, to the attachment target object, the display label having a back side on which an adhesive layer is formed, and then forming a slit serving as the separation and rupture portion on the display label.

摘要翻译： 用于处理显示标签的分离和断裂部分的方法是在附接到附接目标对象的显示标签上形成用于在显示标签与附接目标分离时破坏显示标签的分离和破裂部分的方法 目的。 该方法包括将具有背面的形成有粘合剂层的显示标签附着到附着对象物上，然后在显示标签上形成用作分离破裂部的狭缝。

公开(公告)号：US07194571B2

公开(公告)日：2007-03-20

申请号：US11037261

申请日：2005-01-19

申请人： Naoki Yada ,  Eiichi Ishikawa

发明人： Naoki Yada ,  Eiichi Ishikawa

IPC分类号： G06F12/00

CPC分类号： G06F9/328 ,  G06F3/0605 ,  G06F3/0652 ,  G06F3/0679 ,  G06F8/60 ,  G06F9/4401 ,  G06F9/4486

摘要： The present invention provides a microcomputer wherein in a system which needs to respond to events developed at intervals each shorter than an erase/program process time, erase/programming can be effected on an on-chip non-volatile memory as necessary during its processing. An erase and program control program for an electrically erasable and programmable non-volatile memory is configured inclusive of a loop of the application of a high voltage pulse and data verify or the like, for example. If a program jumped to a subroutine for an address specified by a user is programmed in advance during this loop, then a process by a CPU can be temporarily jumped to the subroutine for the user defined address. Thus, erase and programming can be effected on a system which needs to confirm internal and external events every predetermined intervals or a system with a learning function, or the like during the execution of a user program.

摘要翻译： 本发明提供一种微型计算机，其中在需要响应于比擦除/编程处理时间短的间隔发生的事件的系统中，可以在其处理期间根据需要在片上非易失性存储器上进行擦除/编程。 例如，用于电可擦除和可编程非易失性存储器的擦除和程序控制程序被配置为包括应用高压脉冲和数据验证等的循环。 如果在该循环期间程序跳转到用于指定的地址的子程序，则可以暂时将CPU的进程跳转到用户定义地址的子程序。 因此，擦除和编程可以在每个预定间隔需要确认内部和外部事件的系统或具有学习功能的系统等在用户程序执行期间进行。

公开(公告)号：US07057937B1

公开(公告)日：2006-06-06

申请号：US09132085

申请日：1998-08-10

申请人： Kiyoshi Matsubara ,  Masanao Sato ,  Hirofumi Mukai ,  Eiichi Ishikawa

发明人： Kiyoshi Matsubara ,  Masanao Sato ,  Hirofumi Mukai ,  Eiichi Ishikawa

IPC分类号： G11C7/00

CPC分类号： G11C16/102 ,  G11C16/16 ,  G11C16/3436

摘要： A data processing apparatus having a built-in flash memory and being capable of rewriting the built-in flash memory by use of versatilely used PROM writer has a CPU, an electrically rewritable nonvolatile flash memory both formed in a single semiconductor substrate, and is operable in a mode in which the built-in flash memory is rewritable in accordance with commands supplied from a PROM writer. The data processing apparatus has a command latch made externally writable when the above-mentioned operation mode is established, a command analyzer and a sequence controller for controlling a sequence of rewriting the flash memory in accordance with the analysis result. The command analyzer and sequence controller may be realized by the CPU.

摘要翻译： 具有内置闪存并且能够通过使用通用的PROM写入器来重写内置闪速存储器的数据处理装置具有两个形成在单个半导体衬底中的可电可重写的非易失性闪速存储器，并且可操作 在内置闪速存储器根据从PROM写入器提供的命令是可重写的模式。 当建立上述操作模式时，数据处理装置具有可外部写入的命令锁存器，命令分析器和顺序控制器，用于根据分析结果控制重写闪速存储器的顺序。 命令分析器和顺序控制器可以由CPU实现。

公开(公告)号：US07023729B2

公开(公告)日：2006-04-04

申请号：US11004869

申请日：2004-12-07

申请人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

发明人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

IPC分类号： G11C14/00

CPC分类号： G11C16/12 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C16/30

摘要： A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

公开(公告)号：US20050094472A1

公开(公告)日：2005-05-05

申请号：US11004869

申请日：2004-12-07

申请人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

发明人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

IPC分类号： G11C5/14 ,  G11C16/30 ,  G11C5/00

CPC分类号： G11C16/12 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C16/30

摘要： A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations The microcomputer comprises a voltage-clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

摘要翻译： 一种微型计算机，其包括在包括用于低电压操作的外部电源电压的相对宽范围内以稳定的方式电擦除和编程的闪存。微计算机包括电压钳位单元，其包括参考电压产生电路和恒定电压 电压发生电路。 在操作中，电压钳位单元产生对电源电压的低依赖性的电压，并将所产生的电压钳位到在可容忍范围内低于外部单个电源电压的电压电平。 这可防止由钳位电压工作的升压电路（即编程和擦除电压）由外部提供的电压而提升的电压。

公开(公告)号：US06255225B1

公开(公告)日：2001-07-03

申请号：US09359734

申请日：1999-07-23

申请人： Yoshiaki Yamada ,  Eiichi Ishikawa

发明人： Yoshiaki Yamada ,  Eiichi Ishikawa

IPC分类号： H01L21302

CPC分类号： H01L21/0274 ,  G03F7/091 ,  H01L21/312

摘要： A method of forming a resist pattern and a method of manufacturing a semiconductor device using the method of forming the resist pattern, characterized in that a surface of an organic base coating 3 formed on an etched film 2 is reformed depending on properties of a material of a resist film 4, whereby, in dual processes for forming a lower layer of the organic coating provided to process the etched film, an amount of usable resist is increased and an accuracy of dimensions of the etched film after processing can be improved.

摘要翻译： 一种形成抗蚀剂图案的方法和使用形成抗蚀剂图案的方法制造半导体器件的方法，其特征在于，形成在蚀刻膜2上的有机基底涂层3的表面根据材料的性质进行重整 抗蚀剂膜4，由此，在用于形成用于处理蚀刻膜的有机涂层的下层的双重工艺中，可用抗蚀剂的量增加，并且可以提高加工后的蚀刻膜的尺寸精度。