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    Semiconductor integrated circuit having buses with different data transfer rates
    3.
    发明授权
    Semiconductor integrated circuit having buses with different data transfer rates 有权
    具有不同数据传输速率的总线的半导体集成电路

    公开(公告)号：US07821824B2

    公开(公告)日：2010-10-26

    申请号：US12258964

    申请日：2008-10-27

    申请人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

    发明人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

    IPC分类号： G11C16/04

    CPC分类号： G11C16/349 ,  G11C16/06 ,  G11C16/3495

    摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.

    摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数。

    Microcomputer with mode-controlled memory
    4.
    发明授权
    Microcomputer with mode-controlled memory 失效
    具有模式控制存储器的微型计算机

    公开(公告)号：US07277979B2

    公开(公告)日：2007-10-02

    申请号：US10981612

    申请日：2004-11-05

    申请人： Naoki Yada ,  Eiichi Ishikawa

    发明人： Naoki Yada ,  Eiichi Ishikawa

    IPC分类号： G06F12/00

    CPC分类号： G06F8/60 ,  G06F9/4401 ,  G06F13/387

    摘要： A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.

    摘要翻译： 一种能够在不需要安装板上的串行接口的情况下对专用用户通信协议进行板载编程的微型计算机，即使系统失去控制也不会破坏专用用户通信协议代码。 提供除用户垫之外的用户启动垫用于微型计算机的片上非易失性存储器中的用户的编程控制程序。 用户启动垫用作编程专用用户通信协议的垫，并且还提供用于运行程序的用户引导模式。 在此用户启动模式下，用户启动垫无法编程或擦除。 通过分离用户启动垫和用户垫，可以实现能够编程和擦除用户指定的编程的接口，而无需在用户垫上编程专用通信协议。

    Microcomputer and microprocessor having flash memory operable from single external power supply
    5.
    发明申请
    Microcomputer and microprocessor having flash memory operable from single external power supply 失效
    具有从单个外部电源可操作的闪存的微计算机和微处理器

    公开(公告)号：US20070206432A1

    公开(公告)日：2007-09-06

    申请号：US11797579

    申请日：2007-05-04

    申请人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

    发明人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

    IPC分类号： G11C16/06

    CPC分类号： G11C16/12 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C16/30

    摘要： A data processing apparatus supplied a first voltage from outside, includes a CPU, a first voltage generating circuit, a second voltage generating circuit, a clock generating circuit, and, a nonvolatile memory which can be accessed by the CPU. The first voltage generating circuit generates a second voltage, a voltage level of which is lower than that of the first voltage. The clock generating circuit is supplied the second voltage from the first voltage generating circuit and generates a clock signal, and the second voltage generating circuit is supplied the second voltage from the first voltage generating circuit and the clock signal from the clock generating circuit, and generates a second voltage, a voltage level of which is higher than that of the first voltage, for supplying to the nonvolatile memory.

    摘要翻译： 从外部提供第一电压的数据处理装置包括CPU，第一电压产生电路，第二电压产生电路，时钟发生电路和可被CPU访问的非易失性存储器。 第一电压产生电路产生其电压电平低于第一电压的第二电压。 时钟发生电路从第一电压产生电路提供第二电压并产生时钟信号，并且第二电压产生电路从第一电压产生电路提供第二电压和来自时钟发生电路的时钟信号，并产生 其电压电平高于第一电压的第二电压，用于提供给非易失性存储器。

    Microcomputer and microprocessor having flash memory operable from single external power supply
    6.
    发明授权
    Microcomputer and microprocessor having flash memory operable from single external power supply 有权
    具有从单个外部电源可操作的闪存的微计算机和微处理器

    公开(公告)号：US06407959B2

    公开(公告)日：2002-06-18

    申请号：US09874116

    申请日：2001-06-06

    申请人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

    发明人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

    IPC分类号： G11C700

    CPC分类号： G11C16/30 ,  G11C5/14 ,  G11C5/145

    摘要： A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

    摘要翻译： 微型计算机包括闪存，其在相对较宽的外部电源电压范围内以稳定的方式被电擦除和编程，包括用于低电压操作的外部电源电压。 该微型计算机包括一个包括一个参考电压产生电路和一个恒压发生电路的电压钳位单元。 在操作中，电压钳位单元产生对电源电压的低依赖性的电压，并将所产生的电压钳位到在可容忍范围内低于外部单个电源电压的电压电平。 这可防止由钳位电压工作的升压电路（即编程和擦除电压）由外部提供的电压而提升的电压。

    Microcomputer and microprocessor having flash memory operable from single external power supply
    7.
    发明授权
    Microcomputer and microprocessor having flash memory operable from single external power supply 有权
    具有从单个外部电源可操作的闪存的微计算机和微处理器

    公开(公告)号：US6154412A

    公开(公告)日：2000-11-28

    申请号：US397851

    申请日：1999-09-17

    申请人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

    发明人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

    IPC分类号： G11C5/14 ,  G11C16/30 ,  G11C7/00

    CPC分类号： G11C16/30 ,  G11C5/14 ,  G11C5/145

    摘要： A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

    摘要翻译： 一种微型计算机，包括闪存，其在相对较宽范围的外部电源电压（包括用于低电压操作的电源电压）内以稳定的方式电气地编程。微计算机包括电压钳位单元，其包括参考电压产生电路和恒定电压 发电电路。 在操作中，电压钳位单元产生对电源电压的低依赖性的电压，并将所产生的电压钳位到在可容许范围内低于外部单个电源电压的电压电平。这防止了升压电路升压的电压 在钳位电压（即编程和擦除电压）上操作，取决于外部提供的电压。

    Method of forming a fine resist pattern using an alkaline film covered photoresist
    8.
    发明授权
    Method of forming a fine resist pattern using an alkaline film covered photoresist 失效
    使用碱性膜覆盖的光致抗蚀剂形成精细抗蚀剂图案的方法

    公开(公告)号：US5554489A

    公开(公告)日：1996-09-10

    申请号：US353256

    申请日：1994-12-02

    申请人： Takeo Ishibashi ,  Eiichi Ishikawa ,  Itaru Kanai

    发明人： Takeo Ishibashi ,  Eiichi Ishikawa ,  Itaru Kanai

    IPC分类号： G03F7/26 ,  G03F7/09 ,  H01L21/027 ,  H01L21/30 ,  G03K5/00

    CPC分类号： G03F7/091 ,  H01L21/0276 ,  Y10S430/151

    摘要： A forming method of a fine resist pattern improve so as to form a fine pattern of high accuracy can be obtained. A positive-type photoresist 1 including naphthoquinone diazide and novolak resin is applied on a substrate. An anti-reflection film adjusted to alkalinity is applied on positive-type photoresist 1. Positive-type photoresist 1 on which anti-reflection film 9 is applied is selectively irradiated. Positive-type photoresist 1 is developed.

    摘要翻译： 可以提高精细抗蚀剂图案的形成方法，从而形成高精度的精细图案。 将包含萘醌二叠氮化物和酚醛清漆树脂的正型光致抗蚀剂1涂布在基材上。 在正性光致抗蚀剂1上涂布调整为碱度的防反射膜。选择性地照射涂有防反射膜9的正型光致抗蚀剂1。 显影正型光致抗蚀剂1。

    Dynamic random access memory device having reduced stepped portions
    9.
    发明授权
    Dynamic random access memory device having reduced stepped portions 失效
    动态随机存取存储器件具有减小的阶梯部分

    公开(公告)号：US5539231A

    公开(公告)日：1996-07-23

    申请号：US397341

    申请日：1995-03-02

    申请人： Toshifumi Suganaga ,  Eiichi Ishikawa

    发明人： Toshifumi Suganaga ,  Eiichi Ishikawa

    IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108 ,  H01L27/148 ,  H01L29/768

    CPC分类号： H01L27/10852 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76897 ,  H01L23/53271 ,  H01L28/40 ,  H01L2924/0002

    摘要： A first conductive layer and a second conductive layer are formed apart from each other on a surface of a semiconductor substrate. A first contact hole for exposing a surface of first conductive layer is formed in an interlayer insulating film. A first interconnection layer is buried in first contact hole so as to be in contact with first conductive layer. The position of the surface of first interconnection layer is the same as or lower than the surface of interlayer insulating film. The surface of first interconnection layer is covered with an insulating film. A second contact hole for exposing a surface of second conductive layer is provided in interlayer insulating film. A second conductive layer is connected to second conductive layer through second contact hole.

    摘要翻译： 第一导电层和第二导电层在半导体衬底的表面上彼此分开形成。 用于暴露第一导电层的表面的第一接触孔形成在层间绝缘膜中。 第一互连层埋在第一接触孔中以与第一导电层接触。 第一互连层的表面的位置与层间绝缘膜的表面相同或更低。 第一互连层的表面被绝缘膜覆盖。 用于暴露第二导电层的表面的第二接触孔设置在层间绝缘膜中。 第二导电层通过第二接触孔连接到第二导电层。

    Semiconductor integrated circuit
    10.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US08576643B2

    公开(公告)日：2013-11-05

    申请号：US13368461

    申请日：2012-02-08

    申请人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

    发明人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

    IPC分类号： G11C7/00

    CPC分类号： G11C16/349 ,  G11C16/06 ,  G11C16/3495

    摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has a maximum variation width of a threshold voltage for memorizing an information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.

    摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息集的阈值电压的最大变化宽度。 可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数。