公开(公告)号：US07330051B1

公开(公告)日：2008-02-12

申请号：US11354766

申请日：2006-02-14

申请人： Joseph Huang ,  Chiakang Sung ,  Michael H. M. Chu ,  Yan Chong

发明人： Joseph Huang ,  Chiakang Sung ,  Michael H. M. Chu ,  Yan Chong

IPC分类号： H03K19/173

CPC分类号： H03K19/17744

摘要： The amount of simultaneous switching noise generated through the operation of a programmable device can be reduced by reducing the number of pins switching at the same time. An I/O bank can include a number of I/O pin subsets, or DQS groups, each programmed to switch at a different time so that the switching times of the various pins can be staggered for each system clock cycle. Programmable delay elements can be used to control the delay of each subset. The programmable elements can be placed between the system clock and the output registers in order to delay the receiving of the clock signal by the registers and therefore delaying the switching of the output buffers. The programmable delay elements also can be placed between the output registers and the output buffers in order to delay the receiving of the output data by, and subsequent switching of, the output buffers.

摘要翻译： 通过可编程器件的操作产生的同时开关噪声的量可以通过减少引脚数目同时减少。 I / O bank可以包括多个I / O引脚子集或DQS组，每组都被编程为在不同的时间切换，使得各个引脚的切换时间可以在每个系统时钟周期内交错。 可编程延迟元件可用于控制每个子集的延迟。 可编程元件可以放置在系统时钟和输出寄存器之间，以便延迟寄存器对时钟信号的接收，从而延迟输出缓冲器的切换。 可编程延迟元件也可以放置在输出寄存器和输出缓冲器之间，以便延迟输出缓冲器的输出数据的接收和随后的切换。

公开(公告)号：US07324405B1

公开(公告)日：2008-01-29

申请号：US11368369

申请日：2006-03-03

申请人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

发明人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

IPC分类号： G11C8/00

CPC分类号： H03K5/135 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  H03M9/00

摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.

摘要翻译： 用于在高速数据接口处过滤信号的电路，方法和装置。 一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。 时钟输入端口与输入单元连接或断开。 当接收到数据脉冲串时，时钟输入端口连接到输入单元。 当数据突发结束时，时钟输入端口与输入单元断开连接。 在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。 该信号随后改变指示正在接收最后一个数据位的状态。 当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。

公开(公告)号：US07200769B1

公开(公告)日：2007-04-03

申请号：US10037861

申请日：2002-01-02

申请人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

发明人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

IPC分类号： G06F1/04

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/108 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091

摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.

摘要翻译： 用于延迟多数据速率接口的时钟信号的方法和装置。 一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。 还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。 第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。 第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

公开(公告)号：US06992947B1

公开(公告)日：2006-01-31

申请号：US10696209

申请日：2003-10-28

申请人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong

发明人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong

IPC分类号： G11C8/00

CPC分类号： H03K19/1776 ,  G11C8/16

摘要： Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

公开(公告)号：US06961280B1

公开(公告)日：2005-11-01

申请号：US10731279

申请日：2003-12-08

申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Johnson Tan

发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Johnson Tan

IPC分类号： G06F12/08 ,  G11C8/00 ,  G11C8/06 ,  G11C8/10

CPC分类号： G11C8/06 ,  G06F12/0895 ,  G11C8/10

摘要： Techniques are provided for recycling addresses in memory blocks. Address signals in memory blocks are stored temporarily in a set of parallel coupled address registers. The address registers transfer the address signals to an address decoder block, which decodes the address signals. The address decoder block transfers the decoded addresses to a memory array. A stall state occurs when the cache memory block needs a new set of data to replace the old set of data. Address signals are stored in the address registers during the stall state by coupling each register's output to its data input using a series of multiplexers. The multiplexers are controlled by an address stall signal that indicates the onset and the end of a stall state. After the end of a stall state, the address registers store the next address signal received at the memory block.

摘要翻译： 提供技术来回收内存块中的地址。 存储器块中的地址信号被临时存储在一组并行耦合的地址寄存器中。 地址寄存器将地址信号传送到地址解码块，对地址信号进行解码。 地址解码器块将解码的地址传送到存储器阵列。 当缓存存储块需要一组新的数据来替换旧的数据集时，会发生停顿状态。 通过使用一系列多路复用器将每个寄存器的输出耦合到其数据输入，地址信号在失速状态下存储在地址寄存器中。 多路复用器由指示失速状态的开始和结束的地址停止信号控制。 在停止状态结束后，地址寄存器存储在存储块处接收的下一个地址信号。

公开(公告)号：US06911860B1

公开(公告)日：2005-06-28

申请号：US10037716

申请日：2001-11-09

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Philip Pan ,  Yan Chong ,  In Whan Kim ,  Gopinath Rangan ,  Tzung-Chin Chang

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Philip Pan ,  Yan Chong ,  In Whan Kim ,  Gopinath Rangan ,  Tzung-Chin Chang

IPC分类号： H03K17/35

CPC分类号： H03K17/6871 ,  H03K3/356113 ,  H03K17/063

摘要： A switch circuit selectively provides a reference voltage, needed in some I/O standards, to a logic device. The circuit receives a dedicated power supply that is different from the device's I/O supply. It may also include a level shifting circuit for converting a master control signal having a logic level determined by a first supply to a first control signal having a logic level determined by the dedicated supply. The switch circuit also includes a transmission switch that passes the reference voltage to an output in response to at least the first control signal. The transmission switch may be a CMOS transmission gate with at least one NMOS transistor controlled by the first control signal in parallel with at least one PMOS transistor controlled by a second control signal, complementary to the first. The second control signal may be generated by another level shifting circuit and have a logic level determined by the I/O supply.

摘要翻译： 开关电路选择性地将某些I / O标准所需的参考电压提供给逻辑器件。 该电路接收与设备的I / O电源不同的专用电源。 其还可以包括电平移位电路，用于将具有由第一电源确定的逻辑电平的主控制信号转换成具有由专用电源确定的逻辑电平的第一控制信号。 开关电路还包括传输开关，其响应于至少第一控制信号将参考电压传递到输出。 传输开关可以是CMOS传输门，其中至少一个NMOS晶体管由第一控制信号控制，与由与第一控制信号互补的第二控制信号控制的至少一个PMOS晶体管并联。 第二控制信号可以由另一电平移位电路产生并具有由I / O电源确定的逻辑电平。

公开(公告)号：US06731142B1

公开(公告)日：2004-05-04

申请号：US10412705

申请日：2003-04-10

申请人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

发明人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

IPC分类号： H03K2100

CPC分类号： H03M9/00 ,  G06F1/08 ,  H03K5/135

摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

摘要翻译： 公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。 时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。 在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。 移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。 来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。 延迟电路延迟输入参考时钟。 在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。 由于所有输出路径中的延迟相匹配，所以偏斜最小化。

公开(公告)号：US06731137B1

公开(公告)日：2004-05-04

申请号：US10131976

申请日：2002-04-24

申请人： Gopinath Rangan ,  Chiakang Sung ,  Xiaobao Wang ,  Philip Pan ,  Yan Chong ,  In Whan Kim ,  Khai Nguyen ,  Bonnie Wang ,  Tzung-Chin Chang ,  Joseph Huang

发明人： Gopinath Rangan ,  Chiakang Sung ,  Xiaobao Wang ,  Philip Pan ,  Yan Chong ,  In Whan Kim ,  Khai Nguyen ,  Bonnie Wang ,  Tzung-Chin Chang ,  Joseph Huang

IPC分类号： H03K3356

CPC分类号： H04L25/0264 ,  H03K5/08

摘要： The present invention encompasses a bus hold and weak pull-up circuit. A resistor having a first node and a second node is coupled to a bi-directional I/O pin at the first node. The weak pull-up circuit is directly coupled to the resistor at the first node. The bus hold circuit is coupled to the resistor at the second node.

摘要翻译： 本发明包括总线保持和弱上拉电路。 具有第一节点和第二节点的电阻器耦合到第一节点处的双向I / O引脚。 弱上拉电路直接耦合到第一节点处的电阻器。 总线保持电路耦合到第二节点处的电阻器。

公开(公告)号：US06549045B1

公开(公告)日：2003-04-15

申请号：US10043620

申请日：2002-01-11

申请人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

发明人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

IPC分类号： H03K2100

CPC分类号： H03M9/00 ,  G06F1/08 ,  H03K5/135

摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

摘要翻译： 公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。 时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。 在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。 移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。 来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。 延迟电路延迟输入参考时钟。 在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。 由于所有输出路径中的延迟相匹配，所以偏斜最小化。

公开(公告)号：US08624647B2

公开(公告)日：2014-01-07

申请号：US12690064

申请日：2010-01-19

申请人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

发明人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/151 ,  H03K5/1534 ,  H03K2005/00019

摘要： Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

摘要翻译： 公开了用于校正集成电路（IC）中的占空比失真的电路和方法。 IC包括被耦合以接收时钟信号的分离器电路。 时钟信号分为两个不同的时钟信号。 其中一个时钟信号是另一个的反转版本。 延迟电路耦合到每个时钟信号。 每个延迟电路产生相应时钟信号的延迟版本。 耦合校正器电路以接收时钟信号的延迟版本。 校正器电路产生具有校正占空比的时钟输出信号。