公开(公告)号：US08507384B2

公开(公告)日：2013-08-13

申请号：US13238192

申请日：2011-09-21

申请人： Hongbin Zhu

发明人： Hongbin Zhu

IPC分类号： H01L21/311

CPC分类号： H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/76816 ,  H01L27/115 ,  H01L27/118

摘要： Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch.

公开(公告)号：US20110312171A1

公开(公告)日：2011-12-22

申请号：US12820214

申请日：2010-06-22

申请人： Chan Lim ,  Jennifer Lequn Liu ,  Brian Dolan ,  Saurabh Keshav ,  Hongbin Zhu

发明人： Chan Lim ,  Jennifer Lequn Liu ,  Brian Dolan ,  Saurabh Keshav ,  Hongbin Zhu

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823456 ,  H01L21/28114 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31155 ,  H01L27/11568 ,  H01L29/517

摘要： Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric. The stack is etched at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material. Individual of the gate lines have laterally projecting feet which include the high-k dielectric. After etching the stack to form the gate lines, ions are implanted into an implant region which includes the high-k dielectric of the laterally projecting feet. The ions are chemically inert to the high-k dielectric. The ion implanted high-k dielectric of the projecting feet is etched selectively relative to portions of the high-k dielectric outside of the implant region.

摘要翻译： 方法包括在半导体材料上形成电荷存储晶体管栅叠层。 一个这样的堆叠包括隧道电介质，隧道电介质上的电荷存储材料，电荷存储材料上的高k电介质，以及高k电介质上的导电控制栅极材料。 该堆叠至少蚀刻到隧道电介质以在半导体材料上形成多个电荷存储晶体管栅极线。 栅极线的单独具有横向突出的脚，其包括高k电介质。 在蚀刻堆叠以形成栅极线之后，将离子注入到包括横向突出的脚的高k电介质的植入区域中。 离子对高k电介质是化学惰性的。 选择性地相对于植入区域外的高k电介质的部分蚀刻投影脚的离子注入的高k电介质。

公开(公告)号：US20110248385A1

公开(公告)日：2011-10-13

申请号：US13162889

申请日：2011-06-17

申请人： Hongbin Zhu ,  Jeremy Madsen

发明人： Hongbin Zhu ,  Jeremy Madsen

IPC分类号： H01L23/485 ,  H01L29/06

CPC分类号： H01L21/31122 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76816 ,  H01L2924/0002 ,  Y10T428/265 ,  H01L2924/00

摘要： A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or symmetrical features using a symmetrical photomask, depending on which process flow is chosen. The resulting features which are fabricated use spacers formed around a patterned material. If one particular etch is used to remove a base material, symmetrical features result. If two particular etches are used to remove the base material, asymmetrical features remain.

摘要翻译： 在制造半导体器件期间图案化材料的方法使用对称光掩模来选择性地形成不对称特征或对称特征，这取决于选择哪个工艺流程。 所制造的特征使用围绕图案化材料形成的间隔物。 如果使用特定的蚀刻来去除基底材料，则产生对称的特征。 如果使用两个特殊的蚀刻来去除基材，则不对称的特征保留。

公开(公告)号：US20090239382A1

公开(公告)日：2009-09-24

申请号：US12053513

申请日：2008-03-21

申请人： Hongbin Zhu

发明人： Hongbin Zhu

IPC分类号： H01L21/027

CPC分类号： H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/76816 ,  H01L27/115 ,  H01L27/118

摘要： Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch.

摘要翻译： 提供电路材料处理方法。 在至少一种这样的方法中，衬底设置有多个上覆间隔物。 间隔件具有基本上直的内侧壁和弯曲的外侧壁。 增加材料形成在多个间隔件上，使得间隔件的内侧壁或外侧壁选择性地膨胀。 增加材料可以桥接相邻内侧对的上部，以限制内侧壁之间的沉积。 增强材料被选择性地蚀刻以形成具有内侧壁或外侧壁的期望增加的增强间隔物的图案。 然后可以通过一系列选择性蚀刻将增加的间隔物的图案转移到基底，使得在基底中形成的特征实现期望的间距。

公开(公告)号：US20140167131A1

公开(公告)日：2014-06-19

申请号：US13716287

申请日：2012-12-17

申请人： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A. Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

发明人： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A. Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC分类号： H01L29/788 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

摘要： A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

摘要翻译： 制造三维存储器结构的方法可以包括产生包括导电源层，第一绝缘层，选择栅极源层和第二绝缘层以及阵列堆叠的层叠。 然后可以使用导电源层作为终止蚀刻层来产生通过层叠层的孔。 源材料可以具有不比用于产生孔的蚀刻工艺的绝缘材料的蚀刻速率快33％的蚀刻速率。 然后，半导体材料的柱可以填充孔，使得半导体材料的柱与导电源层电接触。

公开(公告)号：US08696922B2

公开(公告)日：2014-04-15

申请号：US12489062

申请日：2009-06-22

申请人： Hongbin Zhu ,  Mark Kiehlbauch ,  Alex Schrinsky

发明人： Hongbin Zhu ,  Mark Kiehlbauch ,  Alex Schrinsky

IPC分类号： C23F1/00 ,  H01L21/311

CPC分类号： H01L21/32136 ,  H01L27/11521

摘要： A platinum-comprising material is plasma etched by being exposed to a plasma etching chemistry that includes CHCl3, CO2 and O2. In one embodiment, a method of processing a semiconductor substrate in the fabrication of integrated circuitry includes forming metallic platinum-comprising nanoparticles over a material. A portion of the nanoparticles is masked and another portion of the nanoparticles is unmasked. The unmasked portion of the metallic platinum-comprising nanoparticles is plasma etched using a plasma etching chemistry comprising CHCl3, CO2 and O2. Other embodiments are disclosed.

摘要翻译： 通过暴露于包括CHCl 3，CO 2和O 2的等离子体蚀刻化学品来等离子体蚀刻包含铂的材料。 在一个实施例中，在集成电路的制造中处理半导体衬底的方法包括在材料上形成包含金属的纳米颗粒。 纳米颗粒的一部分被掩蔽并且纳米颗粒的另一部分未被掩蔽。 使用包括CHCl 3，CO 2和O 2的等离子体蚀刻化学品等离子体蚀刻含金属铂纳米颗粒的未掩模部分。 公开了其他实施例。

公开(公告)号：US08409457B2

公开(公告)日：2013-04-02

申请号：US12201744

申请日：2008-08-29

申请人： Zishu Zhang ,  Hongbin Zhu ,  Anton deVilliers ,  Alex Schrinsky

发明人： Zishu Zhang ,  Hongbin Zhu ,  Anton deVilliers ,  Alex Schrinsky

IPC分类号： C03C15/00

CPC分类号： G03F7/40 ,  G03F7/0035

摘要： A method of forming a photoresist-comprising pattern on a substrate includes forming a patterned first photoresist having spaced first masking shields in at least one cross section over a substrate. The first masking shields are exposed to a fluorine-containing plasma effective to form a hydrogen and fluorine-containing organic polymer coating about outermost surfaces of the first masking shields. A second photoresist is deposited over and in direct physical touching contact with the hydrogen and fluorine-containing organic polymer coating. The second photoresist which is in direct physical touching contact with the hydrogen and fluorine-containing organic polymer coating is exposed to a pattern of actinic energy and thereafter spaced second masking shields are formed in the one cross section which comprise the second photoresist and correspond to the actinic energy pattern. The first and second masking shields together form at least a part of a photoresist-comprising pattern on the substrate. Other embodiments are disclosed.

摘要翻译： 在衬底上形成含光致抗蚀剂的图案的方法包括在衬底上的至少一个横截面上形成具有间隔开的第一掩蔽屏蔽的图案化的第一光致抗蚀剂。 第一掩蔽屏蔽暴露于含氟等离子体中，有效地在第一掩蔽屏蔽件的最外表面上形成氢和含氟有机聚合物涂层。 第二光致抗蚀剂沉积在氢和含氟有机聚合物涂层上并与其直接物理接触接触。 与氢和含氟有机聚合物涂层直接物理接触接触的第二光致抗蚀剂暴露于光化能的图案，此后在包含第二光致抗蚀剂的一个横截面中形成间隔开的第二掩蔽屏蔽，并对应于 光化能量模式。 第一和第二掩蔽屏蔽一起在衬底上形成包含光致抗蚀剂的图案的至少一部分。 公开了其他实施例。

公开(公告)号：US08030218B2

公开(公告)日：2011-10-04

申请号：US12053513

申请日：2008-03-21

申请人： Hongbin Zhu

发明人： Hongbin Zhu

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC分类号： H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/76816 ,  H01L27/115 ,  H01L27/118

摘要： Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch.

摘要翻译： 提供电路材料处理方法。 在至少一种这样的方法中，衬底设置有多个上覆间隔物。 间隔件具有基本上直的内侧壁和弯曲的外侧壁。 增加材料形成在多个间隔件上，使得间隔件的内侧壁或外侧壁选择性地膨胀。 增加材料可以桥接相邻内侧对的上部，以限制内侧壁之间的沉积。 增强材料被选择性地蚀刻以形成具有内侧壁或外侧壁的期望增加的增强间隔物的图案。 然后可以通过一系列选择性蚀刻将增加的间隔物的图案转移到基底，使得在基底中形成的特征实现期望的间距。

公开(公告)号：US20110237929A1

公开(公告)日：2011-09-29

申请号：US13062649

申请日：2009-09-08

申请人： Zhengrong Liang ,  Su Wang ,  Chaijie Duan ,  Hongbin Zhu ,  Xianfeng Gu

发明人： Zhengrong Liang ,  Su Wang ,  Chaijie Duan ,  Hongbin Zhu ,  Xianfeng Gu

IPC分类号： A61B5/055

CPC分类号： A61B5/055 ,  A61B5/1075 ,  A61B5/411 ,  G01R33/5602 ,  G01R33/5608

摘要： Disclosed is a method and apparatus for detection of a bladder wall tumor. Layers of a bladder wall are created by magnetic resonance imaging. A group of voxels having a lowest intensity is identified in a layer and an energy function modification enlarges the layer of the bladder wall. A partial volume image segmentation obtains tissue type mixture percentages in each voxel near inner and outer borders of the bladder wall in the layer of the bladder wall to obtain a bladder wall thickness. A range of uncertainty at the inner and outer borders of the bladder wall is obtained, and integration is performed of the bladder wall thickness along a path starting at a point on the outer border and ending at a corresponding point on the inner border.

摘要翻译： 公开了一种用于检测膀胱壁肿瘤的方法和装置。 膀胱壁层由磁共振成像产生。 在层中识别具有最低强度的一组体素，并且能量功能修改扩大了膀胱壁的层。 部分体积图像分割在膀胱壁层中的膀胱壁的内外边界附近的每个体素中获得组织类型混合物百分比，以获得膀胱壁厚度。 在膀胱壁的内外边界处获得一系列不确定性，并且沿着从外边界上的点开始并且在内边界上的对应点处开始的路径执行囊壁厚度的整合。

公开(公告)号：US07898019B2

公开(公告)日：2011-03-01

申请号：US12331059

申请日：2008-12-09

申请人： David J. Keller ,  Hongbin Zhu ,  Alex J. Schrinsky

发明人： David J. Keller ,  Hongbin Zhu ,  Alex J. Schrinsky

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11524

摘要： Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.

摘要翻译： 一些实施例包括形成具有与离选择栅极更远的其它NAND串门不同的宽度的与选择栅极最接近的NAND串栅极的NAND单元单元的方法。 一些实施方案包括利用包含HBr和O 2的蚀刻以将图案扩展通过含碳层。 图案化的含碳层可用于对NAND单元单元栅极进行图案化。 一些实施方案包括具有图案化含碳层的结构，其限定具有与离选择栅极更远的其它NAND串栅极不同宽度的最接近选择栅极的NAND串栅极的NAND单元单元。