公开(公告)号：US08173507B2

公开(公告)日：2012-05-08

申请号：US12820214

申请日：2010-06-22

申请人： Chan Lim ,  Jennifer Lequn Liu ,  Brian Dolan ,  Saurabh Keshav ,  Hongbin Zhu

发明人： Chan Lim ,  Jennifer Lequn Liu ,  Brian Dolan ,  Saurabh Keshav ,  Hongbin Zhu

IPC分类号： H01L21/8247

CPC分类号： H01L21/823456 ,  H01L21/28114 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31155 ,  H01L27/11568 ,  H01L29/517

摘要： Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric. The stack is etched at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material. Individual of the gate lines have laterally projecting feet which include the high-k dielectric. After etching the stack to form the gate lines, ions are implanted into an implant region which includes the high-k dielectric of the laterally projecting feet. The ions are chemically inert to the high-k dielectric. The ion implanted high-k dielectric of the projecting feet is etched selectively relative to portions of the high-k dielectric outside of the implant region.

摘要翻译： 方法包括在半导体材料上形成电荷存储晶体管栅叠层。 一个这样的堆叠包括隧道电介质，隧道电介质上的电荷存储材料，电荷存储材料上的高k电介质，以及高k电介质上的导电控制栅极材料。 该堆叠至少蚀刻到隧道电介质以在半导体材料上形成多个电荷存储晶体管栅极线。 栅极线的单独具有横向突出的脚，其包括高k电介质。 在蚀刻堆叠以形成栅极线之后，将离子注入到包括横向突出的脚的高k电介质的植入区域中。 离子对高k电介质是化学惰性的。 选择性地相对于植入区域外的高k电介质的部分蚀刻投影脚的离子注入的高k电介质。

公开(公告)号：US10597527B2

公开(公告)日：2020-03-24

申请号：US15851615

申请日：2017-12-21

申请人： Hongbin Zhu

发明人： Hongbin Zhu ,  Hope Lewis ,  Bozhao Shao

IPC分类号： B01D17/04 ,  C08G83/00 ,  C08G63/668 ,  C08G73/02 ,  C08L79/02 ,  C08L67/00 ,  C08L71/00 ,  C10G33/04 ,  C08G65/26

摘要： This invention provides a composite type heavy oil demulsifier and its preparation methods. The demulsifier includes two effective constituents. The constituent I is an amino nonionic dendritic polyether and the constituent II is a dendritic ester acid. The structural formula is presented as Formula I and II, respectively. The demulsifier has good abilities in interfacing between oil and water and reducing viscosity. It has good demulsification performance in breaking crude oil emulsion and is useful in heavy crude oil production and petroleum refining.

公开(公告)号：US20190194449A1

公开(公告)日：2019-06-27

申请号：US15851615

申请日：2017-12-21

申请人： Hongbin Zhu

发明人： Hongbin Zhu ,  Hope Lewis ,  Bozhao Shao

IPC分类号： C08L67/02 ,  C08L71/00 ,  C10G33/04 ,  B01D17/04

摘要： This invention provides a composite type heavy oil demulsifier and its preparation methods. The demulsifier includes two effective constituents. The constituent I is an amino nonionic dendritic polyether and the constituent II is a dendritic ester acid. The structural formula is presented as Formula I and II, respectively. The demulsifier has good abilities in interfacing between oil and water and reducing viscosity. It has good demulsification performance in breaking crude oil emulsion and is useful in heavy crude oil production and petroleum refining.

公开(公告)号：US20120009793A1

公开(公告)日：2012-01-12

申请号：US13238192

申请日：2011-09-21

申请人： Hongbin Zhu

发明人： Hongbin Zhu

IPC分类号： H01L21/311

CPC分类号： H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/76816 ,  H01L27/115 ,  H01L27/118

摘要： Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch.

摘要翻译： 提供电路材料处理方法。 在至少一种这样的方法中，衬底设置有多个上覆间隔物。 间隔件具有基本上直的内侧壁和弯曲的外侧壁。 增加材料形成在多个间隔件上，使得间隔件的内侧壁或外侧壁选择性地膨胀。 增加材料可以桥接相邻内侧对的上部，以限制内侧壁之间的沉积。 增强材料被选择性地蚀刻以形成具有内侧壁或外侧壁的期望增加的增强间隔物的图案。 然后可以通过一系列选择性蚀刻将增加的间隔物的图案转移到基底，使得在基底中形成的特征实现期望的间距。

公开(公告)号：US20110183269A1

公开(公告)日：2011-07-28

申请号：US12693321

申请日：2010-01-25

申请人： Hongbin Zhu

发明人： Hongbin Zhu

IPC分类号： G03F7/20 ,  G03F7/00

CPC分类号： G03F7/405 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31138

摘要： Some embodiments include methods of forming patterns. Photoresist features may be formed over a base, with the individual photoresist features having heights and widths. The photoresist features may be exposed to a combination of chloroform, oxidant and additional carbon-containing material besides chloroform to reduce the widths of the photoresist features while substantially maintaining the heights of the photoresist features. The photoresist features may then be used as a mask to pattern the underlying base, and/or spacers may be formed to be aligned to sidewalls of the photoresist features, and the spacers may be used as the mask to pattern the underlying base.

摘要翻译： 一些实施例包括形成图案的方法。 可以在基底上形成光刻胶特征，其中各个光致抗蚀剂特征具有高度和宽度。 光致抗蚀剂特征可以暴露于氯仿，氧化剂和除了氯仿之外的另外的含碳材料的组合，以减少光致抗蚀剂特征的宽度，同时基本上保持光致抗蚀剂特征的高度。 然后可以将光致抗蚀剂特征用作掩模以对下面的基底进行图案化，和/或可以将间隔物形成为与光致抗蚀剂特征的侧壁对准，并且间隔物可以用作掩模以对下面的基底进行图案化。

公开(公告)号：US07985681B2

公开(公告)日：2011-07-26

申请号：US11766931

申请日：2007-06-22

申请人： Hongbin Zhu ,  Jeremy Madsen

发明人： Hongbin Zhu ,  Jeremy Madsen

IPC分类号： H01L21/461

CPC分类号： H01L21/31122 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76816 ,  H01L2924/0002 ,  Y10T428/265 ,  H01L2924/00

摘要： A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or symmetrical features using a symmetrical photomask, depending on which process flow is chosen. The resulting features which are fabricated use spacers formed around a patterned material. If one particular etch is used to remove a base material, symmetrical features result. If two particular etches are used to remove the base material, asymmetrical features remain.

摘要翻译： 在制造半导体器件期间图案化材料的方法使用对称光掩模来选择性地形成不对称特征或对称特征，这取决于选择哪个工艺流程。 所制造的特征使用围绕图案化材料形成的间隔物。 如果使用特定的蚀刻来去除基底材料，则产生对称的特征。 如果使用两个特殊的蚀刻来去除基材，则不对称的特征保留。

公开(公告)号：US20080169496A1

公开(公告)日：2008-07-17

申请号：US11652903

申请日：2007-01-12

申请人： David J. Keller ,  Hongbin Zhu ,  Alex J. Schrinsky

发明人： David J. Keller ,  Hongbin Zhu ,  Alex J. Schrinsky

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11524

摘要： Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.

摘要翻译： 一些实施例包括形成具有与离选择栅极更远的其它NAND串门不同的宽度的与选择栅极最接近的NAND串栅极的NAND单元单元的方法。 一些实施方案包括利用包含HBr和O 2 2的蚀刻来将图案延伸穿过含碳层。 图案化的含碳层可用于对NAND单元单元栅极进行图案化。 一些实施方案包括具有图案化含碳层的结构，其限定具有与离选择栅极更远的其它NAND串栅极不同宽度的最接近选择栅极的NAND串栅极的NAND单元单元。

公开(公告)号：US07476588B2

公开(公告)日：2009-01-13

申请号：US11652903

申请日：2007-01-12

申请人： David J. Keller ,  Hongbin Zhu ,  Alex J. Schrinsky

发明人： David J. Keller ,  Hongbin Zhu ,  Alex J. Schrinsky

IPC分类号： H01L21/336 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L27/115 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11524

摘要： Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.

摘要翻译： 一些实施例包括形成具有与离选择栅极更远的其它NAND串门不同的宽度的与选择栅极最接近的NAND串栅极的NAND单元单元的方法。 一些实施方案包括利用包含HBr和O 2的蚀刻以将图案扩展通过含碳层。 图案化的含碳层可用于对NAND单元单元栅极进行图案化。 一些实施方案包括具有图案化含碳层的结构，其限定具有与离选择栅极更远的其它NAND串栅极不同宽度的最接近选择栅极的NAND串栅极的NAND单元单元。

公开(公告)号：US6153061A

公开(公告)日：2000-11-28

申请号：US257572

申请日：1999-02-25

申请人： Yonhua Tzeng ,  Hongbin Zhu

发明人： Yonhua Tzeng ,  Hongbin Zhu

IPC分类号： C23C14/06 ,  C23C14/34 ,  C23C14/35

CPC分类号： C23C14/345 ,  C23C14/0647 ,  C23C14/355

摘要： A method of forming cubic phase boron nitride films in which a hexagonal boron nitride film target is positioned in front of an RF magnetron sputtering gun and is impacted with ions to cause atoms of boron and nitrogen to be sputtered away from the target and toward a substrate. At the same time, electrons are emitted into the system by an electron emitter, which electrons are attracted to the substrate as the boron and nitrogen atoms are being deposited on the substrate. The electrons cause the boron and nitrogen atoms to be reformed on the substrate as cubic phase boron nitride while suppressing the formation of other, less desirable forms of boron nitride films.

摘要翻译： 一种形成立方氮化硼膜的方法，其中六方氮化硼膜靶位于RF磁控溅射枪的前面，并且与离子冲击以使硼和氮的原子溅射离开靶并朝向衬底 。 同时，电子通过电子发射器发射到系统中，当硼和氮原子沉积在衬底上时，电子被吸引到衬底上。 电子使硼和氮原子在基板上重整为立方相氮化硼，同时抑制形成其它不理想形式的氮化硼膜。

公开(公告)号：US20180108669A1

公开(公告)日：2018-04-19

申请号：US15296858

申请日：2016-10-18

申请人： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

发明人： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC分类号： H01L27/115 ,  H01L29/10 ,  H01L29/51 ,  H01L21/311 ,  H01L21/28 ,  H01L21/285

CPC分类号： H01L27/11556 ,  H01L21/28273 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/31111 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/513

摘要： Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.