公开(公告)号：US4923762A

公开(公告)日：1990-05-08

申请号：US382108

申请日：1989-07-19

申请人： Hiroshi Ishikawa ,  Naoki Gunji ,  Yoshinori Hoshino ,  Taro Ohyama

发明人： Hiroshi Ishikawa ,  Naoki Gunji ,  Yoshinori Hoshino ,  Taro Ohyama

IPC分类号： B05D7/16 ,  B21D22/20 ,  C09D5/00 ,  C09D5/38

CPC分类号： B05D7/16 ,  B21D22/201 ,  C09D5/002 ,  C09D5/38 ,  B05D2252/10 ,  Y10T428/12049 ,  Y10T428/12063 ,  Y10T428/12139 ,  Y10T428/12146 ,  Y10T428/12569

摘要： A precoated steel sheet for a two-piece can, which comprises: a steel sheet; a precoating film formed on one surface of the steel sheet, which is to be the outer surface of a two-piece can, by applying a precoating composition onto the one surface of the steel sheet and curing same; and another precoating film formed on the other surface of the steel sheet, which is to be the inner surface of the two-piece can, by applying another precoating composition onto the other surface of the steel sheet and curing same. The above-mentioned precoating composition comprises a thermosetting coating material and an internal lubricant having a content ratio within the range of from 0.1 to 30 weight parts relative to 100 weight parts of a resin as a solid content in the thermosetting coating material. The above-mentioned another precoating composition comprises the above-mentioned thermosetting coating material and an aluminum powder having a content ratio within the range of from 10 to 400 weight parts relative to 100 weight parts of the resin as the solid content in the thermosetting material.

公开(公告)号：US08813553B2

公开(公告)日：2014-08-26

申请号：US13285191

申请日：2011-10-31

申请人： Yoshinori Hoshino

发明人： Yoshinori Hoshino

IPC分类号： G01N19/04 ,  G01N3/08

CPC分类号： G01N19/04 ,  G01N2203/0025 ,  G01N2203/0605

摘要： A device for a peel test. The device includes: a gripping member to grip an end of a test film to be peeled off a test object; a movable member linearly moving in a direction to or away from the gripping member; a holding member for the movable member capable of linearly moving in a direction along a peel surface of the test object while holding the test object; a moving mechanism configured to move the movable member linearly; a load measuring unit configured to measure a load applied to the gripping member; a first conversion mechanism to convert the linear motion of the movable member to rotational power, and output the rotational power; and a second conversion mechanism to convert the rotational power output from the first conversion mechanism to the linear motion of the holding member relative to the movable member.

摘要翻译： 剥离试验装置。 该装置包括：抓握构件，用于夹持待测试物体剥离的测试膜的端部; 可动构件，其在朝向或远离所述夹持构件的方向上直线移动; 用于可移动部件的保持部件，能够在保持被检体的同时沿着被检体的剥离面的方向直线移动; 移动机构，其构造成使所述可动构件线性移动; 负载测量单元，被配置为测量施加到所述夹持构件的负载; 第一转换机构，用于将可动构件的直线运动转换成旋转动力，并输出旋转动力; 以及第二转换机构，用于将从第一转换机构输出的旋转动力转换成保持构件相对于可动构件的直线运动。

公开(公告)号：US07679136B2

公开(公告)日：2010-03-16

申请号：US11334446

申请日：2006-01-19

申请人： Tsuyoshi Kachi ,  Yoshinori Hoshino

发明人： Tsuyoshi Kachi ,  Yoshinori Hoshino

IPC分类号： H01L23/62

CPC分类号： H01L29/7811 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： The on-resistance of a semiconductor device having a power transistor with a trench gate structure is reduced. A power MIS-FET with a trench gate structure is so formed that the relation expressed as 0≦b≦a holds, where a is the distance between an end of an interlayer insulating layer over the upper face of a semiconductor region for source and the end (position on the periphery of a trench) of the upper face of the semiconductor region for source farther from the gate electrode; and b is the length of the overlap between the interlayer insulating layer and the upper face of the semiconductor region for source. (b is the distance between the position of the end of the interlayer insulating layer over the upper face of the semiconductor region for source and position on the periphery of a trench). As a result, the area of contact between source pads and the semiconductor regions for source is increased, and further the distance between the source pads and a channel forming region can be shortened. Therefore, the on-resistance of the power MIS-FET with a trench gate structure can be reduced.

摘要翻译： 具有沟槽栅极结构的功率晶体管的半导体器件的导通电阻减小。 具有沟槽栅极结构的功率MIS-FET被形成为使得表示为0＆nlE; b＆nlE; a的关系成立，其中a是源极半导体区域的上表面上的层间绝缘层的端部与 用于远离栅电极的源极的半导体区域的上表面的端部（沟槽的外围的位置）; b是层间绝缘层与源极半导体区域的上表面之间的重叠长度。 （b是在源极的半导体区域的上表面上的层间绝缘层的端部的位置与沟槽的周边上的位置之间的距离）。 结果，源极焊盘与源极半导体区域之间的接触面积增加，并且可以缩短源极焊盘与沟道形成区域之间的距离。 因此，可以减小具有沟槽栅极结构的功率MIS-FET的导通电阻。

公开(公告)号：US07084055B2

公开(公告)日：2006-08-01

申请号：US10930845

申请日：2004-09-01

申请人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

发明人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

IPC分类号： H01L21/4763

CPC分类号： H01L27/10885 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76837 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/90

摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is a method in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g., a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at a first temperature, and the structure is subjected to RTA (heat treatment) at a second temperature higher than the first temperature (e.g., 750° C.). Via holes are then formed in the high density plasma silicon oxide film, and first and second conductive films are then formed, the first conductive film being formed in the via holes and at a third temperature lower than the first temperature. The first and second conductive layers are then polished to remain selectively within the via holes. In heat treating the high density plasma silicon oxide film, the temperature is raised from the first temperature to the second temperature at a maximum speed of 60° C./second or less.

摘要翻译： 期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。 为了实现这一点，公开了一种方法，其中例如将高密度等离子体氧化硅膜沉积在布线（例如，连接到DRAM存储器的存储器单元选择MISFET的源极和漏极区域的位线） 在第一温度下，通过高密度等离子体CVD技术，在高于第一温度（例如750℃）的第二温度下对该结构进行RTA（热处理）。 然后在高密度等离子体氧化硅膜中形成通孔，然后形成第一和第二导电膜，第一导电膜形成在通孔中并且在比第一温度低的第三温度下形成。 然后抛光第一和第二导电层以选择性地保持在通孔内。 在高密度等离子体氧化硅膜的热处理中，以60℃/秒以下的最高速度将温度从第一温度升高到第二温度。

公开(公告)号：US06803271B2

公开(公告)日：2004-10-12

申请号：US10187003

申请日：2002-07-02

申请人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

发明人： Tsuyoshi Fujiwara ,  Katsuyuki Asaka ,  Yasuhiro Nariyoshi ,  Yoshinori Hoshino ,  Kazutoshi Oomori

IPC分类号： H01L218242

CPC分类号： H01L27/10885 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76837 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/90

摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, an HDP silicone oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor to be connected to the other of the source and drain region of the memory cell selection MISFET is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.

摘要翻译： 期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。 为了实现这一点，HDP硅氧化物膜通过高密度等离子体CVD技术沉积在与DRAM存储单元的存储单元选择MISFET的源极和漏极区域连接的位线上，结构是 在750℃下进行RTA（热处理）。抛光表面，然后形成要连接到存储单元选择MISFET的源极和漏极区域中的另一个的电容器。 结果，即使当用作电容器的电容绝缘膜的氧化钽膜进行热处理时，施加在位线上的膜应力减小，位线的断裂和分离是 防止了

公开(公告)号：US5227729A

公开(公告)日：1993-07-13

申请号：US674327

申请日：1991-04-15

申请人： Yoshinori Hoshino

发明人： Yoshinori Hoshino

IPC分类号： G01R31/00 ,  G01R31/327 ,  G05B19/048 ,  G05B19/05 ,  H01H47/00

CPC分类号： H01H47/004 ,  G01R31/3278

摘要： A fusion detecting system for relays is provided for detecting a fusion of relay contacts. Two fully-interlocked or semi-interlocked relays are connected in such a manner that they operate under identical conditions, and a fused state is detected based on the states of signals sent from series-connected make contacts and series-connected break contacts of the two relays. In the case of semi-interlocked relays (R1, R2), if a make contact (r12) is fused during a current supply to a coil, the other contact (r22) remains in an open state or at a make-contact side after the current supply to the coil is cut off, and if a break contact (r11) is fused, the other contact (r21) remains in an open state or at break-contact side after a current is supplied to the relay coil. Accordingly, by using two semi-interlocked relays under identical conditions and connecting same such that the make contacts and the break contacts are individually connected in series, a fusion of the relays can be detected based on signals sent from the contacts. A fusion of fully-interlocked relays can be detected in a like manner.

公开(公告)号：US08770079B2

公开(公告)日：2014-07-08

申请号：US13483821

申请日：2012-05-30

申请人： Kenji Baba ,  Yuji Hasebe ,  Yoshinori Hoshino

发明人： Kenji Baba ,  Yuji Hasebe ,  Yoshinori Hoshino

IPC分类号： B26F1/04

CPC分类号： B26F1/04 ,  B26D5/16 ,  B26D7/1818 ,  B26F1/14 ,  B26F1/16 ,  G03G15/6582 ,  G03G2215/00818 ,  Y10T83/8828 ,  Y10T83/8843 ,  Y10T83/943 ,  Y10T408/858

摘要： A sheet hole punching device has a device frame; a plurality of punching members arranged in first and second groups, and arranged linearly on the device frame; a driving rotation shaft; a driving motor reciprocally rotating the driving rotation shaft; a gear mechanism transmitting a rotation of the driving rotation shaft; cam mechanisms converting the rotational movement; and a motor control device. The gearing mechanism includes drive gears disposed on the drive rotational shaft, and receiving gears disposed on the punching members to engage with the drive gears. The cam mechanisms include cam followers and cylindrical cams. The cylindrical cam has a V-shaped groove cam to reciprocate each of the punching members between an upper dead point and a lower dead point. The punching members are rotated in one direction to punch holes in first sheets, and subsequently rotated in a reverse direction to punch holes in following sheets.

摘要翻译： 片孔冲孔装置具有装置框架; 多个冲压构件，其布置在第一组和第二组中，并且线性地布置在装置框架上; 驱动旋转轴; 使驱动旋转轴往复旋转的驱动马达; 传递驱动旋转轴的旋转的齿轮机构; 转动旋转运动的凸轮机构; 和电动机控制装置。 齿轮传动装置包括设置在驱动旋转轴上的驱动齿轮，以及设置在冲压部件上以与驱动齿轮接合的齿轮。 凸轮机构包括凸轮从动件和圆柱凸轮。 圆柱形凸轮具有V形凹槽凸轮，以在上死点和下死点之间使每个冲压构件往复运动。 冲压构件沿一个方向旋转以在第一片材中冲孔，并且随后沿相反方向旋转以在随后的片材中穿孔。

公开(公告)号：US20060157779A1

公开(公告)日：2006-07-20

申请号：US11334446

申请日：2006-01-19

申请人： Tsuyoshi Kachi ,  Yoshinori Hoshino

发明人： Tsuyoshi Kachi ,  Yoshinori Hoshino

IPC分类号： H01L29/94

CPC分类号： H01L29/7811 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： The on-resistance of a semiconductor device having a power transistor with a trench gate structure is reduced. A power MIS-FET with a trench gate structure is so formed that the relation expressed as 0≦b≦a holds, where a is the distance between an end of an interlayer insulating layer over the upper face of a semiconductor region for source and the end (position on the periphery of a trench) of the upper face of the semiconductor region for source farther from the gate electrode; and b is the length of the overlap between the interlayer insulating layer and the upper face of the semiconductor region for source. (b is the distance between the position of the end of the interlayer insulating layer over the upper face of the semiconductor region for source and position on the periphery of a trench). As a result, the area of contact between source pads and the semiconductor regions for source is increased, and further the distance between the source pads and a channel forming region can be shortened. Therefore, the on-resistance of the power MIS-FET with a trench gate structure can be reduced.

摘要翻译： 具有沟槽栅极结构的功率晶体管的半导体器件的导通电阻减小。 具有沟槽栅极结构的功率MIS-FET被形成为使得表示为0 <= b <= a的关系成立，其中a是源极半导体区域的上表面之间的层间绝缘层的端部之间的距离 以及用于远离栅电极的源极的半导体区域的上表面的端部（沟槽的外围的位置）; b是层间绝缘层与源极半导体区域的上表面之间的重叠长度。 （b是在源极的半导体区域的上表面上的层间绝缘层的端部的位置与沟槽的周边上的位置之间的距离）。 结果，源极焊盘与源极半导体区域之间的接触面积增加，并且可以缩短源极焊盘与沟道形成区域之间的距离。 因此，可以减小具有沟槽栅极结构的功率MIS-FET的导通电阻。

公开(公告)号：US4861647A

公开(公告)日：1989-08-29

申请号：US167355

申请日：1988-03-14

申请人： Hiroshi Ishikawa ,  Hiroshi Takano ,  Ryosuke Ohtomo ,  Yoshinori Hoshino ,  Taro Ohyama

发明人： Hiroshi Ishikawa ,  Hiroshi Takano ,  Ryosuke Ohtomo ,  Yoshinori Hoshino ,  Taro Ohyama

IPC分类号： B05D7/16 ,  C09D5/00 ,  C09D7/12 ,  C09D163/00

CPC分类号： B05D7/16 ,  C09D163/00 ,  C09D5/002 ,  C09D7/125 ,  C09D7/1283 ,  C08L23/06 ,  C08L23/12 ,  Y10T428/1359 ,  Y10T428/24975 ,  Y10T428/265 ,  Y10T428/3154 ,  Y10T428/31544 ,  Y10T428/31699 ,  Y10T428/31714 ,  Y10T428/31801

摘要： A precoating for a two-piece can, comprising a thermosetting coating and an internal lubricant. The internal lubricant comprises a modified hydrocarbon wax having a structure in which a plurality of repeated units of a fluorine atoms substituted olefin are combined with a hydrocarbon wax.

摘要翻译： 用于两片罐的预涂层，包括热固性涂层和内部润滑剂。 内部润滑剂包括具有多个重复单元的氟原子取代的烯烃与烃蜡组合的结构的改性烃蜡。

公开(公告)号：US08741699B2

公开(公告)日：2014-06-03

申请号：US13479360

申请日：2012-05-24

申请人： Daisuke Arai ,  Yoshito Nakazawa ,  Ikuo Hara ,  Tsuyoshi Kachi ,  Yoshinori Hoshino ,  Tsuyoshi Tabata

发明人： Daisuke Arai ,  Yoshito Nakazawa ,  Ikuo Hara ,  Tsuyoshi Kachi ,  Yoshinori Hoshino ,  Tsuyoshi Tabata

IPC分类号： H01L21/332

CPC分类号： H01L29/66325 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/7395

摘要： Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

摘要翻译： 提供了能够提高能够降低稳定损耗，关断时间和关断损耗的IGBT的产量的技术。 在形成在基板的主表面上的层间绝缘膜中形成开口时，在氮化硅膜上一次停止对PSG膜的叠层绝缘膜，SOG膜和氧化硅膜的蚀刻。 然后，依次蚀刻氮化硅膜和氧化硅膜以形成开口。 结果，防止了开口穿过厚度为20至100nm的n型源极层和p +型发射极层并到达衬底。