公开(公告)号：US07889537B2

公开(公告)日：2011-02-15

申请号：US12118064

申请日：2008-05-09

申请人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

发明人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

IPC分类号： G11C11/00 ,  G11C17/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/72

摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

摘要翻译： 本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件 系列。 根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。 然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

公开(公告)号：US07768844B2

公开(公告)日：2010-08-03

申请号：US12202601

申请日：2008-09-02

申请人： Satoru Takase ,  Takuya Futatsuyama

发明人： Satoru Takase ,  Takuya Futatsuyama

IPC分类号： G11C7/00

CPC分类号： G11C8/12 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

摘要： This disclosure concerns a memory including memory cell arrays including word lines extending in a first direction, bit lines extending in a second direction crossing the first direction, and memory cells provided to respectively correspond to cross-points in form of a lattice constituted by the word lines and the bit lines; sense amplifiers provided to respectively correspond to the bit lines and reading data stored in the memory cells; and bit line drivers provided to the bit lines and operating the bit lines when data is written to the memory cells, wherein the bit line drivers access the memory cells adjacent to a first memory cell diagonally with respect to the form of the lattice for writing the data to the adjacent memory cells during a data write operation without changing data stored in the memory cells adjacent to the first memory cell in the first and the second directions.

摘要翻译： 本公开涉及包括存储单元阵列的存储器，该存储器单元阵列包括沿第一方向延伸的字线，沿与第一方向交叉的第二方向延伸的位线，以及提供分别对应于由该字形成的格子形式的交点的存储单元 线和位线; 提供的读出放大器分别对应于位线和读取存储在存储器单元中的数据; 和位线驱动器，当数据被写入存储单元时，位线驱动器被提供给位线并操作位线，其中位线驱动器相对于格子的形式访问与第一存储器单元相对的第一存储器单元， 在数据写入操作期间向相邻存储器单元提供数据，而不改变存储在与第一和第二方向上的第一存储单元相邻的存储单元中的数据。

公开(公告)号：US07729178B2

公开(公告)日：2010-06-01

申请号：US11849891

申请日：2007-09-04

申请人： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

发明人： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

IPC分类号： G11C7/10

CPC分类号： G11C16/102

摘要： The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

摘要翻译： 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US20080081467A1

公开(公告)日：2008-04-03

申请号：US11842615

申请日：2007-08-21

申请人： Takuya Futatsuyama

发明人： Takuya Futatsuyama

IPC分类号： H01L21/44

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/105

摘要： A first insulating film, a second insulating film, a first resist pattern is formed on a semiconductor substrate, the second insulating film is etched to form a second-insulating-film pattern, a third insulating film is deposited over the second-insulating-film pattern to form a third-insulating-film pattern, the first insulating film is etched to form a first-insulating-film pattern, a fourth insulating film and a second resist pattern is formed over the first-insulating-film pattern, fourth insulating film is etched to form a fourth-insulating-film pattern, a fifth insulating film is deposited over the fourth-insulating-film pattern to form a fifth-insulating-film pattern, line parts of first-insulating-film pattern is etched to form a first-insulating-film pattern for wiring, a wiring film is formed over the first-insulating-film pattern for wiring, the wiring film is removed until the first-insulating-film pattern for wiring is exposed to form a wiring pattern.p

摘要翻译： 在半导体衬底上形成第一绝缘膜，第二绝缘膜，第一抗蚀剂图案，蚀刻第二绝缘膜以形成第二绝缘膜图案，在第二绝缘膜上沉积第三绝缘膜 形成第三绝缘膜图案，第一绝缘膜被蚀刻以形成第一绝缘膜图案，第四绝缘膜和第二抗蚀剂图案形成在第一绝缘膜图案上，第四绝缘膜 被蚀刻以形成第四绝缘膜图案，在第四绝缘膜图案上沉积第五绝缘膜以形成第五绝缘膜图案，蚀刻第一绝缘膜图案的线部分以形成 用于布线的第一绝缘膜图案，布线膜形成在用于布线的第一绝缘膜图案上，布线膜被去除，直到用于布线的第一绝缘膜图案暴露以形成布线图案

公开(公告)号：US07352625B2

公开(公告)日：2008-04-01

申请号：US11196445

申请日：2005-08-04

申请人： Takuya Futatsuyama ,  Ken Takeuchi

发明人： Takuya Futatsuyama ,  Ken Takeuchi

IPC分类号： G11C11/34

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C16/0483

摘要： A semiconductor memory device disclosed herein includes: a first select gate line, a gate electrode of a first select transistor connected to the first select gate line; a second select gate line, a gate electrode of a second select transistor connected to the second select gate line; and word lines between the first select gate line and the second select gate line, gate electrodes of memory cells being respectively connected to the word lines, wherein when data in a memory cell connected to a first adjacent word line which is adjacent to the first select gate line is read, a voltage of the second select gate line is increased after a voltage of the first select gate line is increased, and when data in a memory cell connected to a second adjacent word line adjacent to the second select gate line is read, the voltage of the first select gate line is increased after the voltage of the second gate line is increased.

摘要翻译： 本文公开的半导体存储器件包括：第一选择栅极线，连接到第一选择栅极线的第一选择晶体管的栅电极; 第二选择栅极线，连接到第二选择栅极线的第二选择晶体管的栅电极; 和第一选择栅极线与第二选择栅极线之间的字线，存储单元的栅电极分别连接到字线，其中当连接到与第一选择栅极相邻的第一相邻字线的存储单元中的数据时 在第一选择栅极线的电压增加之后第二选择栅极线的电压被增加，并且当连接到与第二选择栅极线相邻的第二相邻字线的存储单元中的数据被读取时，第二选择栅极线的电压被增加 在第二栅极线的电压增加之后第一选择栅极线的电压增加。

公开(公告)号：US07274603B2

公开(公告)日：2007-09-25

申请号：US11330143

申请日：2006-01-12

申请人： Takuya Futatsuyama ,  Ken Takeuchi

发明人： Takuya Futatsuyama ,  Ken Takeuchi

IPC分类号： G11C7/00

CPC分类号： G11C16/08 ,  G11C16/0483 ,  H03K19/01855

摘要： A level shifter circuit comprises a first output MIS transistor of a first conductivity, and a second output MIS transistor of a second conductivity type having a second threshold voltage. The former has a first threshold voltage, wherein the output voltage is positively fed back to a gate terminal and the power supply voltage is applied to a first terminal to generate a first voltage at a second terminal. In the latter, the first voltage is applied to a first terminal and a second voltage is applied to a gate terminal to control conduction to generate the output voltage at a second terminal. The first and second charge type MIS transistors and the discharge MIS transistor are connected between the first terminal and gate terminal of the second output MIS transistor to charge or discharge the potential of the gate terminal of the second output MIS transistor.

摘要翻译： 电平移位器电路包括具有第一导电率的第一输出MIS晶体管和具有第二阈值电压的第二导电类型的第二输出MIS晶体管。 前者具有第一阈值电压，其中输出电压被正向反馈到栅极端子，并且将电源电压施加到第一端子以在第二端子处产生第一电压。 在后者中，第一电压被施加到第一端子，并且第二电压被施加到栅极端子以控制导通以在第二端子处产生输出电压。 第一和第二充电型MIS晶体管和放电MIS晶体管连接在第二输出MIS晶体管的第一端子和栅极端子之间，以对第二输出MIS晶体管的栅极端子的电位进行充电或放电。

公开(公告)号：US20070025152A1

公开(公告)日：2007-02-01

申请号：US11495463

申请日：2006-07-31

申请人： Takuya Futatsuyama

发明人： Takuya Futatsuyama

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： A non-volatile semiconductor memory device comprise a memory cell array having a plurality of memory cell units each having a plurality of electrically-programmable memory cell connected in series, a plurality of word lines each connected to each of control gates of said plurality of memory cells, said plurality of word lines including a selected word line connected to a control gate of selected one of said memory cells for programming, and a plurality of unselected word lines different from said selected word line, a bit line connected to one end of said memory cell unit, and a source line connected to another end of the memory cell unit, wherein, when data is programmed into the selected memory cells, a first potential is supplied to said selected word line, and a first unselected word line adjacent, toward a source line side, to said selected word line is set to floating state, and thereafter, a second potential which is higher than said first potential is supplied to said selected word line.

摘要翻译： 非易失性半导体存储器件包括具有多个存储单元单元的存储单元阵列，每个存储单元单元具有串联连接的多个电可编程存储单元，多个字线各自连接到所述多个存储器的每个控制栅极 所述多个字线包括连接到所选择的一个所述存储器单元的用于编程的控制栅极的选定字线以及与所述选择字线不同的多个未选择字线，连接到所述存储单元的一端的位线 存储单元单元和连接到存储单元单元的另一端的源极线，其中当数据被编程到所选择的存储单元中时，第一电位被提供给所述选择的字线，并且第一未选字线相邻，朝向 源极线侧到所述选择的字线被设置为浮置状态，此后，高于所述第一电位的第二电位被提供给所选择的 字线。

公开(公告)号：US07142453B2

公开(公告)日：2006-11-28

申请号：US11196460

申请日：2005-08-04

申请人： Takuya Futatsuyama

发明人： Takuya Futatsuyama

IPC分类号： G11C16/04

CPC分类号： G11C16/08

摘要： A semiconductor memory device disclosed herein comprises: a memory cell array including memory blocks, each memory block including memory cells arranged in a matrix and the memory cell array including first select gate transistors to select one or more memory cells; a select gate line configured to input a control signal which controls continuity of the first select gate transistor to a gate of the first select gate transistor, the select gate line being shared between two adjacent memory blocks; and a row select circuit configured to select a memory block of a row designated by an input address signal, wherein the row select circuit comprises: only one transfer transistor provided between the select gate line and a non-select signal line to which a non-select signal is supplied, the non-select signal being the control signal indicating non-selection; and a select gate control circuit configured to bring the transfer transistor into conduction to supply the non-select signal to the select gate line when both the two adjacent memory blocks are not selected.

公开(公告)号：US20060197136A1

公开(公告)日：2006-09-07

申请号：US11346293

申请日：2006-02-03

申请人： Takuya Futatsuyama ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Atsushi Maesono ,  Ayako Nakano ,  Tadahito Fujisawa

发明人： Takuya Futatsuyama ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Atsushi Maesono ,  Ayako Nakano ,  Tadahito Fujisawa

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11517

摘要： According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines; and electrical connections for connection said word lines and sources or drains of said first transistors, said electrical connections being formed of both first wirings of a first wiring layer formed above said first gate wiring layer and second wirings of a second wiring layers formed above said first wiring layer.

摘要翻译： 根据本发明，实现了高可靠性的NAND型闪速存储器。 它提供一种半导体存储器件，包括：多个存储单元; 由第一栅极布线层形成的多个字线; 用于向所述字线提供电压的多个第一晶体管; 以及用于连接所述字线和所述第一晶体管的源极或漏极的电连接，所述电连接由形成在所述第一栅极布线层上方的第一布线层的第一布线和形成在所述第一晶体管上方的第二布线层的第二布线形成 接线层。

公开(公告)号：US20060172567A1

公开(公告)日：2006-08-03

申请号：US11329101

申请日：2006-01-11

申请人： Takuya Futatsuyama

发明人： Takuya Futatsuyama

IPC分类号： H05K1/00

CPC分类号： H01L23/5226 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises: a plurality of first wiring lines formed in a first layer with a first wiring width and a first wiring space; a plurality of second wiring lines formed in a second layer different from the above-described first layer with a second wiring width and a second wiring space larger than the above-described first wiring width and first wiring space; and a contact plug connecting the first wiring line and second wiring line. The above-described contact plug is formed over a plurality of adjacent ones of the above-described first wiring lines and has a pattern connecting the plurality of adjacent ones of the above-described first wiring lines and one of the above-described second wiring lines.