-
11.发明授权公开(公告)号：US07729370B1
公开(公告)日：2010-06-01
申请号：US11495868
申请日：2006-07-28
Applicant: Jairone A. Orcine , Ricardo H. Bruce
Inventor： Jairone A. Orcine , Ricardo H. Bruce
CPC classification number: H04L49/357 , H04L49/40
Abstract: This invention relates to data networks, and more particularly, to platforms, modules and systems for networking at least one device having Fibre Channel node functionality with another device. Networking of Fibre Channel-enabled devices is provided by an apparatus that includes a circuit board having a first set of signal paths; a first transceiver having a first optical I/O port, a first transceiver output and a first transceiver input; a first I/O connection for coupling to a first Fibre Channel port and for receiving signals transmitted by the first transceiver output via a subset of the first set of signal paths; and a second I/O connection for coupling to a second Fibre Channel port and for receiving signals from the first Fibre Channel Port.
Abstract translation: 本发明涉及数据网络，更具体地说，涉及用于将具有光纤通道节点功能的至少一个设备与另一设备联网的平台，模块和系统。 光纤通道设备的网络由包括具有第一组信号路径的电路板的设备提供; 具有第一光I / O端口，第一收发器输出和第一收发器输入的第一收发器; 第一I / O连接，用于耦合到第一光纤通道端口，以及用于经由第一组信号路径的子集接收由第一收发器输出发送的信号; 以及用于耦合到第二光纤通道端口并用于从第一光纤通道端口接收信号的第二I / O连接。
-
公开(公告)号：US10430303B1
公开(公告)日：2019-10-01
申请号：US15891147
申请日：2018-02-07
Applicant: BITMICRO Networks, Inc.
Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.
-
公开(公告)号：US10120694B2
公开(公告)日：2018-11-06
申请号：US14217365
申请日：2014-03-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Alvin Anonuevo Manlapat , Ian Victor Pasion Beleno
IPC: G06F1/24 , G06F9/44 , G06F9/4401 , G06F1/12
Abstract: A mechanism of booting up a system directly from a storage device and a means of initializing an embedded system prior to activating a CPU is presented. The said system is comprised of one or more CPUs, a reset controller, a storage device controller, one or more direct memory access controllers, a RAM and its controller, a ROM and its controller, a debug interface and a power-on reset (POR) sequencer. The POR sequencer controls the overall boot process of the embedded system. Said sequencer uses descriptors (POR Sequencer descriptors) which are used to update the configuration registers of the system and to enable CPU-independent data transfers with the use of DMA controllers.Using a minimal amount of non-volatile memory for booting up a system brings down costs associated with increased silicon real estate area and power consumption. Capability of pre-initializing the system even before a CPU is brought out of reset provides flexibility and system robustness. Through the use of the Power-On Reset Sequencer module, integrity of program code and user data used in the boot up process can be verified thus providing a resilient boot up sequence.The present invention provides a mechanism for booting up a system using a minimum amount of nonvolatile memory. This method also enables the embedded system to initialize all configuration registers even before any of the CPUs of the system is brought out of reset. The embedded system consists of multiple controller chips or a single controller chip. The embedded system can have a single or multiple central processing units.
-
公开(公告)号：US10078604B1
公开(公告)日：2018-09-18
申请号：US14690349
申请日：2015-04-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Arnaldo Cristobal , Marlon Verdan
CPC classification number: G06F13/24 , G06F9/4825
Abstract: In an embodiment of the invention, a method comprises: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In another embodiment of the invention, an apparatus comprises: an interrupt controller configured to collect a plurality of interrupts and configured to service coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In yet another embodiment of the invention, an article of manufacture comprises: a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired.
-
15.发明授权公开(公告)号：US09952991B1
公开(公告)日：2018-04-24
申请号：US14690339
申请日：2015-04-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Ricardo H. Bruce , Marlon B. Verdan , Rowenah Michelle Jago-on
IPC: G06F5/12 , G06F13/28 , G06F13/40 , H04L12/801 , G06F5/14
CPC classification number: G06F13/28 , G06F5/12 , G06F5/14 , G06F13/4068 , H04L47/10
Abstract: In an embodiment of the invention, a method comprises: fetching a first set of descriptors from a memory device and writing the first set of descriptors to a buffer; retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation; and if space is available in the buffer, fetching a second set of descriptors from the memory device and writing the second set of descriptors to the buffer during or after the processing of the first set of descriptors. In another embodiment of the invention, an apparatus comprises: a fetching module configured to fetch a first set of descriptors from a memory device and to write the first set of descriptors to a buffer; a sequencer configured to retrieve the first set of descriptors from the buffer and to process the first set of descriptors to permit a Direct Memory Access (DMA) operation; and wherein if space is available in the buffer, the fetching module is configured to fetch a second set of descriptors from the memory device and to write the second set of descriptors to the buffer during or after the processing of the first set of descriptors.
-
Patent Agency Ranking
公开(公告)号：US09875205B1
公开(公告)日：2018-01-23
申请号：US14217161
申请日：2014-03-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Ricardo H. Bruce , Jarmie De La Cruz Espuerta , Marlon Basa Verdan
CPC classification number: G06F13/4031 , G06F13/385 , G06F13/4027
Abstract: A large network of memory system is described comprising a plurality of system controllers and flash memory modules, in accordance with an embodiment of the invention. An apparatus is also described comprising a plurality of flash memory modules interconnected with other flash memory modules and to at least one system controller via a point-to-point communication bus topology, in accordance with another embodiment of the invention.
-
公开(公告)号：US09672178B1
公开(公告)日：2017-06-06
申请号：US14687700
申请日：2015-04-15
Applicant: BiTMICRO Networks, Inc.
Inventor： Cyrill C. Ponce , Marizonne O. Fuentes , Gianico G. Noble
CPC classification number: G06F13/37 , G06F3/061 , G06F3/0656 , G06F3/0683 , G06F13/28 , G06F13/287
Abstract: In an embodiment of the invention, a method comprises: A method, comprising: issuing, by a Direct Memory Access (DMA) engine, an update request to a dependency table if the DMA engine has finished executing a first descriptor; and issuing, by the DMA engine, a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the subindex is in the dependency table. In another embodiment of the invention, an apparatus comprises: a Direct Memory Access (DMA) engine configured to issue an update request to a dependency table if the DMA engine has finished executing a first descriptor, and configured to issue a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the subindex is in the dependency table.
-
公开(公告)号：US08788725B2
公开(公告)日：2014-07-22
申请号：US13890229
申请日：2013-05-08
Applicant: BiTMICRO Networks, Inc.
IPC: G06F13/28
CPC classification number: G06F13/1657 , G06F12/00 , G06F12/0246 , G06F13/1673 , G06F13/1684 , G06F13/36
Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.
Abstract translation: 本发明涉及用于在至少一个DMA控制器与至少一个固态半导体存储器件（诸如NAND闪存器件等）之间传送信息的多电平存储器总线系统。 该多电平存储器总线系统包括耦合到中间总线的至少一个DMA控制器; 闪存总线; 以及中间总线和闪存总线之间的闪存缓冲电路。 该多级存储器总线系统可以被设置为支持：n位宽的总线宽度，例如半字节宽度或字节宽度的总线宽度; 中间总线上的可选择的数据采样率，例如单次或双次采样率; 可配置的总线数据速率，例如单，双，四进制或八进制数据采样率; CRC保护; 独家繁忙的机制; 专线忙 或这些的任何组合。
-
19.发明授权公开(公告)号：US08560804B2
公开(公告)日：2013-10-15
申请号：US12882059
申请日：2010-09-14
Applicant: Rolando H. Bruce , Reyjan C. Lanuza , Jose Miguel N. Lukban , Mark Ian A. Arcedera , Ryan C. Chong
Inventor： Rolando H. Bruce , Reyjan C. Lanuza , Jose Miguel N. Lukban , Mark Ian A. Arcedera , Ryan C. Chong
IPC: G06F12/00
CPC classification number: G11C16/14 , G06F3/0679 , G06F12/0246 , G11C16/08 , G11C16/16 , G11C16/20 , G11C16/26
Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
-
公开(公告)号：US08010740B2
公开(公告)日：2011-08-30
申请号：US12323461
申请日：2008-11-25
Applicant: Mark I. Arcedera , Ritchie Babaylan , Reyjan Lanuza
Inventor： Mark I. Arcedera , Ritchie Babaylan , Reyjan Lanuza
IPC: G06F12/00
CPC classification number: G06F12/0246 , G06F2212/7201
Abstract: To optimize memory operations, a mapping table may be used that includes: logical fields representing a plurality of LBA sets, including first and second logical fields for representing respectively first and second LBA sets, the first and second LBA sets each representing a consecutive LBA set; PBA fields representing PBAs, including a first PBA disposed for representing a first access parameter set and a second PBA disposed for representing a second access parameter set, each PBA associated with a physical memory location in a memory store, and these logical fields and PBA fields disposed to associate the first and second LBA sets with the first and second PBAs; and, upon receiving an I/O transaction request associated with the first and second LBA sets, the mapping table causes optimized memory operations to be performed on memory locations respectively associated with the first and second PBAs.
Abstract translation: 为了优化存储器操作，可以使用映射表，其包括：表示多个LBA集合的逻辑字段，包括用于分别表示第一和第二LBA集合的第一和第二逻辑字段，每个表示连续LBA集合的第一和第二LBA集合 ; 表示PBA的PBA字段，包括被设置用于表示第一访问参数集的第一PBA和用于表示第二访问参数集的第二PBA，与存储器存储器中的物理存储器位置相关联的每个PBA，以及这些逻辑字段和PBA字段 被设置为将所述第一和第二LBA组与所述第一和第二PBA相关联; 并且在接收到与第一和第二LBA集相关联的I / O事务请求时，映射表使得优化的存储器操作对分别与第一和第二PBA相关联的存储器位置执行。
-
-
-
-
-
-
-
-
-
Search Results
59
records
(took 0.027 seconds)
