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公开(公告)号：US20240363735A1
公开(公告)日：2024-10-31
申请号：US18763088
申请日：2024-07-03
发明人： Shih-Yao Lin , Chih-Han Lin , Shu-Uei Jang , Ya-Yi Tsai , Chi-Hsiang Chang , Tzu-Chung Wang , Shu-Yuan Ku
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/06 , H01L29/417 , H01L29/78
CPC分类号： H01L29/6681 , H01L21/823431 , H01L29/0649 , H01L29/41791 , H01L29/785
摘要： A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.
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公开(公告)号：US20240363727A1
公开(公告)日：2024-10-31
申请号：US18771597
申请日：2024-07-12
发明人： Huan-Chieh SU , Jia-Chuan YOU , Cheng-Chi CHUANG , Chih-Hao WANG
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/06 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/823418 , H01L21/823431 , H01L21/823481 , H01L29/0649 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device includes a multi-pattern gate (MPG) structure having a gate structure height GSH1 and a gate structure width GSW1; a first sidewall structure on a first vertical side of the MPG structure, and a second sidewall structure on a second vertical side of the MPG structure; a first air spacer adjacent the first sidewall structure, and a second air spacer adjacent the second sidewall structure, each of the first air spacer and the second air spacer having a height ASH1 and a width ASW1; and a first cap structure sealing the first air spacer, and a second cap structure sealing the second air spacer, each of the first cap structure and the second cap structure having a height CH1 and a width CW1. A first expression ASH1>GSH1, a second expression CW1>ASW1, and a third expression GSW1>CW1 are each satisfied.
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公开(公告)号：US20240363722A1
公开(公告)日：2024-10-31
申请号：US18769246
申请日：2024-07-10
发明人： Ting-Ting CHEN , Tsai-Jung Ho , Tsung-Han Ko , Tetsuji Ueno , Yahru Cheng , Chen-Han Wang , Keng-Chu Lin , Shuen-Shin Liang , Tsu-Hsiu Perng
CPC分类号： H01L29/4991 , H01L29/0653 , H01L29/6656
摘要： The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.
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公开(公告)号：US20240363721A1
公开(公告)日：2024-10-31
申请号：US18771578
申请日：2024-07-12
发明人： Po-Chin CHANG , Ming-Huan TSAI , Li-Te LIN , Pinyen LIN
IPC分类号： H01L29/49 , H01L21/8234 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/823431 , H01L21/823475 , H01L29/0847 , H01L29/401 , H01L29/41791 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.
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公开(公告)号：US20240363672A1
公开(公告)日：2024-10-31
申请号：US18363950
申请日：2023-08-02
IPC分类号： H01L27/148 , H01L27/146
CPC分类号： H01L27/14825 , H01L27/14621 , H01L27/14625 , H01L27/14636 , H01L27/14687 , H01L27/14806
摘要： Various embodiments of the present disclosure are directed towards a semiconductor structure including a first substrate comprising a first semiconductor material. A first light sensor is disposed within the first substrate. The first light sensor is configured to absorb electromagnetic radiation within a first wavelength range. A second light sensor is disposed within an absorption structure underlying the first substrate. The second light sensor is configured to absorb electromagnetic radiation within a second wavelength range different from the first wavelength range. The absorption structure underlies the first light sensor and comprises a second semiconductor material different from the first semiconductor material.
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公开(公告)号：US20240363637A1
公开(公告)日：2024-10-31
申请号：US18771450
申请日：2024-07-12
发明人： Guo-Huei WU , Jerry Chang Jui KAO , Chih-Liang CHEN , Hui-Zhong ZHUANG , Jung-Chan YANG , Lee-Chung LU , Xiangdong CHEN
IPC分类号： H01L27/092 , H01L21/8238 , H01L23/528
CPC分类号： H01L27/0924 , H01L21/823821 , H01L21/823871 , H01L23/5286
摘要： A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.
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公开(公告)号：US20240363630A1
公开(公告)日：2024-10-31
申请号：US18770372
申请日：2024-07-11
发明人： Kuan-Ting PAN , Kuo-Cheng CHIANG , Shi Ning JU , Yi-Ruei JHAN , Kuan-Lun CHENG , Chih-Hao WANG
IPC分类号： H01L27/092 , H01L21/02 , H01L21/8238 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L27/092 , H01L21/0259 , H01L21/823807 , H01L21/823878 , H01L29/0665 , H01L29/41733 , H01L29/42392 , H01L29/66742 , H01L29/78696
摘要： Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.
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公开(公告)号：US20240363594A1
公开(公告)日：2024-10-31
申请号：US18768421
申请日：2024-07-10
发明人： Tzu-Hsien Yang , Hiroki Noguchi , Mahmut Sinangil , Yih Wang
IPC分类号： H01L25/065 , H01L21/768 , H01L25/18
CPC分类号： H01L25/0657 , H01L25/18 , H01L21/76898 , H01L2225/06544
摘要： A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.
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公开(公告)号：US20240363587A1
公开(公告)日：2024-10-31
申请号：US18766684
申请日：2024-07-09
发明人： Wen-Wei Shen , Sung-Hui Huang , Shang-Yun Hou
IPC分类号： H01L25/065 , H01L21/56 , H01L21/683 , H01L23/31 , H01L23/538
CPC分类号： H01L25/0655 , H01L21/561 , H01L23/3157 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L21/563 , H01L21/6835 , H01L2221/68331 , H01L2221/68345
摘要： A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant. The electrical connectors are disposed on the protection layer, wherein the interconnection structure is electrically connected to the circuit substrate through the plurality of electrical connectors.
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公开(公告)号：US20240363578A1
公开(公告)日：2024-10-31
申请号：US18768426
申请日：2024-07-10
发明人： Kuang-Wei CHENG , Chyi-Tsong NI
CPC分类号： H01L24/32 , H01L24/27 , H01L24/83 , H01L27/0688 , H01L2224/2745 , H01L2224/27848 , H01L2224/291 , H01L2224/29188 , H01L2224/2919 , H01L2224/32145 , H01L2224/83896
摘要： A method may include forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device, and forming a second ALD bonding layer on a surface of a second semiconductor device. The method may include joining the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer. The method may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer that bonds the first semiconductor device with the second semiconductor device.
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