公开(公告)号：US20230328986A1

公开(公告)日：2023-10-12

申请号：US18070536

申请日：2022-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon KWON ,  Chungki MIN ,  Boun YOON ,  Kihoon JANG

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11556

Abstract: A semiconductor device includes a source structure, first and second stack structures, including first gate electrodes stacked on the source structure to be spaced apart from each other; a dummy structure on the source structure between the first and the second stack structures, and including second gate electrodes stacked to be spaced apart from each other; first separation regions passing through the first and second stack structures, and spaced apart from each other; second separation regions extending between each of the first and second stack structures and the dummy structure; channel structures passing through the first and second stack structures, and respectively including a channel layer, connected to the source structure through the channel layer; and first source contact structures passing through the dummy structure, and respectively including a first contact layer connected to the source structure through a lower surface of the first contact layer.

公开(公告)号：US20230309300A1

公开(公告)日：2023-09-28

申请号：US17705135

申请日：2022-03-25

Applicant: Applied Materials, Inc.

Inventor： Dimitrios Pavlopoulos ,  Rui Cheng ,  Qinghua Zhao ,  Karthik Janakiraman

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L21/02208

Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. Alternating layers of material may be formed on the substrate. One or more recesses may be formed in the alternating layers of material. The methods may include forming a first silicon-containing material. The first silicon-containing material may extend into the one or more recesses formed in the alternating layers of material. The methods may include providing a halogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming a silicon-and-halogen-containing material. The silicon-and-halogen-containing material may overly the first silicon-containing material. The methods may include forming a second silicon-containing material. The second silicon-containing material may overly the silicon-and-halogen-containing material.

公开(公告)号：US20230301089A1

公开(公告)日：2023-09-21

申请号：US17819039

申请日：2022-08-11

Applicant: Kioxia Corporation

Inventor： Tsunehiro INO ,  Yusuke NAKAJIMA ,  Akira TAKASHIMA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: A method for manufacturing an oxide film according to an embodiment includes forming a first film containing aluminum (Al) and nitrogen (N), and forming a second film containing aluminum (Al) and oxygen (O) by oxidizing the first film in an atmosphere containing heavy water (D2O).

公开(公告)号：US20230301085A1

公开(公告)日：2023-09-21

申请号：US17699227

申请日：2022-03-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung CHEN

IPC: H01L27/11524 ,  G11C16/04 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/108

CPC classification number: H01L27/11524 ,  G11C16/0483 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/10805

Abstract: A memory device includes a memory interposer, memory array regions, logic chips, and interconnection lines. The memory array regions are in the memory interposer, in which the memory array regions include at least one memory having NAND architecture. The logic chips are over the memory interposer. The interconnection lines connect the logic chips to each other, and connect the logic chips to the memory array regions.

公开(公告)号：US20230292517A1

公开(公告)日：2023-09-14

申请号：US17816501

申请日：2022-08-01

Applicant: Kioxia Corporation

Inventor： Yusuke OKUMURA

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/5283 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of conductive layers, each of the plurality of conductive layers including a first portion, and a second portion that is thicker than the first portion, a first insulator portion that contacts the second portion of a first conductive layer and the second portion of a second conductive layer, and a second insulator portion that contacts the second portion of a third conductive layer, wherein the second portion of the second conductive layer includes a first sub portion arranged with the second portion of the first conductive layer, and a second sub portion provided between the second portion of the first conductive layer and the second portion of the third conductive layer.

公开(公告)号：US20230292509A1

公开(公告)日：2023-09-14

申请号：US18072276

申请日：2022-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Siyeong YANG ,  Yuyeon KIM ,  Woosung LEE

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/10 ,  H01L23/528 ,  H10B41/35 ,  H10B43/35 ,  H10B43/10

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: A method of manufacturing a semiconductor device includes forming a molded structure by stacking interlayer insulating layers alternately with sacrificial layers on a plate layer, forming channel holes passing through the molded structure, forming channel layers doped with non-conductive impurities in the channel holes, forming a metal layer above the channel holes, forming metal silicide layers on upper ends of the channel layers using the metal layer, crystallizing the channel layers using the metal silicide layers by performing a heat treatment process at a temperature of 800 degrees or more, forming openings penetrating through the molded structure and extending in one direction, removing the sacrificial layers exposed through the openings, and forming gate electrodes, by filling regions from which the sacrificial layers have been removed, with a conductive material. After the crystallizing, the metal silicide layers are located lower than a lowermost gate electrode among the gate electrodes.

公开(公告)号：US20230290739A1

公开(公告)日：2023-09-14

申请号：US17694040

申请日：2022-03-14

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  John Hopkins

IPC: H01L23/00 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  H01L21/28 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/562 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/40114 ,  H01L29/40117 ,  H01L23/53257 ,  H01L23/5226 ,  H01L23/5283

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, the tiers including respective memory cells and control gates for the memory cells; a first pillar extending through the tiers and separated from the control gates, the first pillar including a first dielectric liner portion and a first core portion adjacent the first dielectric liner portion, the first dielectric liner portion and the first core portion extending along a length of the first pillar; and a second pillar extending through the tiers and separated from the control gates, the second pillar including a second dielectric liner portion and a second core portion adjacent the second dielectric liner portion, the second dielectric portion and the second core portion extending along a length of the second pillar, wherein the first core portion and the second core portion have different materials.

公开(公告)号：US20230290409A1

公开(公告)日：2023-09-14

申请号：US17654311

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  John D. Hopkins ,  Jiewei Chen ,  Jordan D. Greenlee

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768

CPC classification number: G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/76843

Abstract: A microelectronic device includes a stack structure, slot structures, and dielectric material. The stack structure includes blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. At least one of the blocks includes an array region including strings of memory cells, and a staircase region including a crest sub-region interposed between a staircase structure and the array region. An uppermost boundary of the tiers within the crest sub-region underlies an uppermost boundary of the tiers within the array region. The slot structures are interposed between the blocks of the stack structure. The dielectric material extends over and between the blocks of the stack structure. A thickness of a portion of the dielectric material overlying the crest sub-region is greater than a thickness of an additional portion of the dielectric material overlying the array region. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20230255031A1

公开(公告)日：2023-08-10

申请号：US18047376

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon ,  Boun Yoon ,  Kihoon Jang

IPC: H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11573 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor device includes a peripheral circuit structure including a substrate, a circuit element on the substrate, connection patterns electrically connected to the circuit element, and a peripheral insulating structure on the circuit element, a memory cell structure on the peripheral circuit structure, the memory cell structure including interlayer insulating layers and gate electrodes alternately stacked on each other, an upper wiring, and a through-contact plug electrically connecting the upper wiring to an upper connection pattern in, which is in an uppermost position of the connection patterns relative to an upper surface of the substrate providing a base reference surface, wherein the peripheral circuit structure further includes a dam structure on the upper connection pattern, the peripheral insulating structure includes a first insulating layer on the circuit element and a side surface of the upper connection pattern and a second insulating layer, a capping layer, and a third insulating layer sequentially stacked on the first insulating layer, wherein the dam structure passes through the second insulating layer and contacts the upper connection pattern, and wherein the through-contact plug includes a lower portion passing through the dam structure and contacting the upper connection pattern and an upper portion on the lower portion.

公开(公告)号：US20230253043A1

公开(公告)日：2023-08-10

申请号：US17668304

申请日：2022-02-09

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  John D. Hopkins ,  Roger W. Lindsay

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: An electronic device comprises a stack comprising tiers of alternating conductive levels and insulative levels overlying a source, slots extending vertically through the stack and dividing the stack into blocks, and support pillars within the slots and extending vertically through the stack. The support pillars exhibit a lateral dimension in a first horizontal direction relatively larger than a lateral dimension of the slots in the first horizontal direction, substantially orthogonal to a second horizontal direction in which the slots extend. Related memory devices, systems, and methods are also described.