公开(公告)号：US20140049415A1

公开(公告)日：2014-02-20

申请号：US13586176

申请日：2012-08-15

Applicant: Steven J. Baumgartner ,  William D. Corti ,  Joseph Natonio

Inventor： Steven J. Baumgartner ,  William D. Corti ,  Joseph Natonio

IPC: H03M1/10

CPC classification number: H03M1/109 ,  H03M1/66

Abstract: A system and method for testing digital to analog converters (DAC) in a serial interface having a comparator to receive an input signal and a local offset signal is disclosed. A first DAC selectably provides one of a global offset to the input signal during a normal mode of operation and a first test signal to the comparator during a test mode of operation. A second DAC selectably provides one of the local offset signals to the comparator during the normal mode of operation and a second test signal to the comparator during the test mode of operation. A test module may cause the first DAC to determine a first test signal to provide to the local offset input of the comparator and may cause the second DAC to incrementally change a test signal provided to the comparator.

Abstract translation: 公开了一种用于在具有用于接收输入信号和本地偏移信号的比较器的串行接口中测试数模转换器（DAC）的系统和方法。 在操作的正常模式期间，第一DAC可选地提供输入信号的全局偏移中的一个，以及在测试操作模式期间向比较器提供第一测试信号。 第二DAC在正常操作模式期间可选地将一个局部偏置信号提供给比较器，并且在测试操作模式期间将第二测试信号提供给比较器。 测试模块可以使得第一DAC确定第一测试信号以提供给比较器的本地偏移输入，并且可以使得第二DAC递增地改变提供给比较器的测试信号。

公开(公告)号：US08510073B2

公开(公告)日：2013-08-13

申请号：US12957277

申请日：2010-11-30

Applicant: Sachin D. Dasnurkar

Inventor： Sachin D. Dasnurkar

IPC: H03M1/10

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: An integrated circuit configured to perform hybrid built in self test (BiST) of analog-to-digital converters (ADCs) is described. The integrated circuit includes an ADC. The integrated circuit also includes a BiST controller that controls the hybrid BiST. The integrated circuit further includes a ramp generator that provides a voltage ramp to the ADC. The integrated circuit also includes a first multiplexer that switches an input for the ADC between the voltage ramp and a voltage reference signal. The integrated circuit further includes feedback circuitry for the ramp generator that maintains a constant ramp slope for the ramp generator. The integrated circuit also includes an interval counter that provides a timing reference.

Abstract translation: 描述了被配置为执行模数转换器（ADC）的混合内置自测（BiST）的集成电路。 集成电路包括一个ADC。 集成电路还包括控制混合BiST的BiST控制器。 集成电路还包括向ADC提供电压斜坡的斜坡发生器。 集成电路还包括第一多路复用器，其在电压斜坡和电压参考信号之间切换ADC的输入。 集成电路还包括用于斜坡发生器的反馈电路，其为斜坡发生器保持恒定的斜坡斜率。 集成电路还包括提供定时参考的间隔计数器。

公开(公告)号：US08400338B2

公开(公告)日：2013-03-19

申请号：US13049286

申请日：2011-03-16

Applicant: David O'Brien

Inventor： David O'Brien

IPC: H03M1/06

CPC classification number: G01R31/2834 ,  G01D5/24452 ,  G01D5/2449 ,  G01R31/31935 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/1095 ,  H03M1/12 ,  H03M1/66

Abstract: Automatic test equipment (ATE) includes circuitry configured to pass a signal in a channel of the ATE, and memory configured to store a first and second correction values. A first correction value is based on a first version of the signal, where the first correction value is for use in correcting static non-linearity associated with the channel. A second correction value is based on a second version of the signal, where the second correction value is for use in correcting dynamic non-linearity associated with the channel. Digital signal processing logic is configured to use the first correction value, the second correction value, and the signal in order to compensate for harmonic distortion from the channel.

Abstract translation: 自动测试设备（ATE）包括被配置为传递ATE的信道中的信号的电路，以及被配置为存储第一和第二校正值的存储器。 第一校正值基于信号的第一版本，其中第一校正值用于校正与通道相关联的静态非线性。 第二校正值基于信号的第二版本，其中第二校正值用于校正与通道相关联的动态非线性。 数字信号处理逻辑被配置为使用第一校正值，第二校正值和信号，以便补偿来自通道的谐波失真。

公开(公告)号：US20120098557A1

公开(公告)日：2012-04-26

申请号：US13144036

申请日：2010-01-12

Applicant: Mathias Krauss ,  Sam Koblenski

Inventor： Mathias Krauss ,  Sam Koblenski

IPC: G01R31/3187

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: Method and system are provided for evaluating linearity of a capacitive-to-digital converter (CDC) of a capacitive sensor integrated circuit chip. The evaluating employs multiple test capacitors, which may be on-chip with the CDC, and includes: obtaining capacitance values for the multiple test capacitors and parasitic capacitances of a first input A and a second input B to the capacitive-to-digital converter; applying the multiple test capacitors in multiple permutations to the first input A and the second input B, and for each of at least some permutations, determining an error between an expected output of the CDC using the obtained capacitance values and an actual measured output of the CDC; and determining linearity error for the CDC using the determined errors for the permutations of applying the multiple test capacitors to the first input A and the second input B of the CDC.

Abstract translation: 提供了用于评估电容式传感器集成电路芯片的电容 - 数字转换器（CDC）的线性度的方法和系统。 该评估采用多个测试电容器，其可以与CDC在芯片上，并且包括：获得多个测试电容器的电容值和第一输入端A和第二输入端B到电容 - 数字转换器的寄生电容; 将多个测试电容器以多个排列施加到第一输入端A和第二输入端B，并且对于至少一些排列中的每一个，使用所获得的电容值确定CDC的期望输出之间的误差和 CDC; 以及使用所确定的用于将多个测试电容器施加到CDC的第一输入A和第二输入B的排列的误差来确定CDC的线性误差。

公开(公告)号：US08106801B2

公开(公告)日：2012-01-31

申请号：US12697435

申请日：2010-02-01

Applicant: Sachin D Dasnurkar

Inventor： Sachin D Dasnurkar

IPC: H03M1/10

CPC classification number: H03K4/501 ,  H03K4/90 ,  H03M1/109 ,  H03M1/12

Abstract: An apparatus configured for built in self test (BiST) of analog-to-digital convertors (ADCs) is described. The apparatus includes an ADC to be tested. The apparatus includes a ramp generator. The ramp generator provides a voltage ramp to the ADC. The apparatus further includes feedback circuitry for the ramp generator. The feedback circuitry maintains a constant ramp slope for the ramp generator. The apparatus includes an interval counter. The interval counter provides a timing reference.

Abstract translation: 描述了配置用于模数转换器（ADC）的内置自检（BiST）的装置。 该装置包括要测试的ADC。 该装置包括斜坡发生器。 斜坡发生器为ADC提供电压斜坡。 该装置还包括用于斜坡发生器的反馈电路。 反馈电路为斜坡发生器保持恒定的斜坡斜率。 该装置包括间隔计数器。 间隔计数器提供定时参考。

公开(公告)号：US20110137604A1

公开(公告)日：2011-06-09

申请号：US12957277

申请日：2010-11-30

Applicant: Sachin D. Dasnurkar

Inventor： Sachin D. Dasnurkar

IPC: H03M1/10 ,  G06F19/00

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: An integrated circuit configured to perform hybrid built in self test (BiST) of analog-to-digital converters (ADCs) is described. The integrated circuit includes an ADC. The integrated circuit also includes a BiST controller that controls the hybrid BiST. The integrated circuit further includes a ramp generator that provides a voltage ramp to the ADC. The integrated circuit also includes a first multiplexer that switches an input for the ADC between the voltage ramp and a voltage reference signal. The integrated circuit further includes feedback circuitry for the ramp generator that maintains a constant ramp slope for the ramp generator. The integrated circuit also includes an interval counter that provides a timing reference.

Abstract translation: 描述了被配置为执行模数转换器（ADC）的混合内置自测（BiST）的集成电路。 集成电路包括一个ADC。 集成电路还包括控制混合BiST的BiST控制器。 集成电路还包括向ADC提供电压斜坡的斜坡发生器。 集成电路还包括第一多路复用器，其在电压斜坡和电压参考信号之间切换ADC的输入。 集成电路还包括用于斜坡发生器的反馈电路，其为斜坡发生器保持恒定的斜坡斜率。 集成电路还包括提供定时参考的间隔计数器。

公开(公告)号：US20110043394A1

公开(公告)日：2011-02-24

申请号：US12859007

申请日：2010-08-18

Applicant: Gianluca Farabegoli ,  Mauro Giacomini ,  Marco Losi

Inventor： Gianluca Farabegoli ,  Mauro Giacomini ,  Marco Losi

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1076 ,  H03M1/109 ,  H03M1/468

Abstract: A circuit including an analog-to-digital converter having a self-test capability that provides not only an indication of failure or performance degradation but also identifies the failed or degraded component or components.

Abstract translation: 包括具有自检能力的模数转换器的电路，其不仅提供故障或性能下降的指示，而且还识别出故障或降级的组件。

公开(公告)号：US20110012617A1

公开(公告)日：2011-01-20

申请号：US12504428

申请日：2009-07-16

Applicant: Yoshikuni GOSHIMA ,  Seiichi Tsuchiya ,  Yoshimasa Sanmiya ,  John William Kay ,  Chising Lai

Inventor： Yoshikuni GOSHIMA ,  Seiichi Tsuchiya ,  Yoshimasa Sanmiya ,  John William Kay ,  Chising Lai

IPC: H01H31/02

CPC classification number: H03M1/109 ,  G03F1/78 ,  H01J2237/1518 ,  H01J2237/2485 ,  H01J2237/3175 ,  H03M1/66

Abstract: A digital-to-analog converter (DAC)/amplifier testing system for use in an electron-beam (e-beam) mask writer, the e-beam mask writer including a plurality of DAC/amplifier circuits to output analog voltage signals, each DAC/amplifier circuit having a first output terminal and a second output terminal, the first output terminals of the plurality of DAC/amplifier circuits being respectively coupled to deflection plates of the e-beam mask writer to provide the output analog voltages as deflection voltages, is provided. The testing system including a summation circuit to sum voltage signals and to output a summation signal indicating the sum of the received analog voltage signals and an analyzer circuit to digitize the summation signal and to detect to compare the digitized summation signal with an error tolerance range to detect whether at least one of the DAC/amplifier circuits is experiencing an operating error.

Abstract translation: 一种用于电子束（电子束）掩模写入器的数模转换器（DAC）/放大器测试系统，电子束掩模写入器包括多个DAC /放大器电路以输出模拟电压信号，每个 DAC /放大器电路具有第一输出端和第二输出端，多个DAC /放大器电路的第一输出端分别耦合到电子束掩模写入器的偏转板，以提供输出模拟电压作为偏转电压， 被提供。 该测试系统包括一个求和电路，用于求和电压信号，并输出一个表示所接收的模拟电压信号和分析电路之和的求和信号，以对加和信号进行数字化，并检测以将数字化求和信号与误差容差范围进行比较 检测至少一个DAC /放大器电路是否正在经历操作错误。

公开(公告)号：US20100102868A1

公开(公告)日：2010-04-29

申请号：US12531830

申请日：2008-03-14

Applicant: Jaeha Kim ,  Hae-Chang Lee ,  Thomas H. Greer, III

Inventor： Jaeha Kim ,  Hae-Chang Lee ,  Thomas H. Greer, III

IPC: G06F1/04

CPC classification number: H03M1/109 ,  G01R31/31725 ,  G01R31/31726 ,  G01R31/31727 ,  H03M1/66

Abstract: A circuit to test phase linearity of a phase synthesizer, which synthesizes an output clock having a phase corresponding to a digital phase value input to the phase synthesizer. A digital counter provides the digital phase value to the phase synthesizer. The digital counter receives a counter clock synchronized with an input clock. The digital phase value is stepped by the digital counter, thereby shifting the frequency of the output clock. The output clock is analyzed with respect to phase linearity of the phase synthesizer to produce a phase linearity analysis output.

Abstract translation: 用于测试相位合成器的相位线性度的电路，其合成具有相应于输入到相位合成器的数字相位值的相位的输出时钟。 数字计数器向相位合成器提供数字相位值。 数字计数器接收与输入时钟同步的计数器时钟。 数字相位值由数字计数器步进，从而移位输出时钟的频率。 对相位合成器的相位线性度分析输出时钟，以产生相位线性分析输出。

公开(公告)号：US07664621B2

公开(公告)日：2010-02-16

申请号：US12118248

申请日：2008-05-09

Applicant: Richard Liggiero, III ,  Alan J. Reiss ,  Philip E. Perkins

Inventor： Richard Liggiero, III ,  Alan J. Reiss ,  Philip E. Perkins

IPC: G01R29/00 ,  G06F13/00

CPC classification number: G01R23/20 ,  G01R31/3167 ,  H03M1/109 ,  H03M1/66

Abstract: The present disclosure relates to a system and method for mapping system transfer functions. Accordingly, some operations may include receiving a first intermediate signal that is at least partially based upon a first reference signal. A second intermediate signal is received that is at least partially based upon a second reference signal. An output signal is generated that is based upon the difference between the first intermediate signal and the second intermediate signal. A first anticipated differential change in the output signal is determined, the first anticipated differential change to occur based upon a transition in the first reference signal. A second anticipated differential change in the output signal is determined, the second anticipated differential change to occur based upon a transition in the second reference signal. Numerous other operations are also within the scope of the present disclosure.

Abstract translation: 本公开涉及一种用于映射系统传送功能的系统和方法。 因此，一些操作可以包括接收至少部分地基于第一参考信号的第一中间信号。 接收至少部分地基于第二参考信号的第二中间信号。 产生基于第一中间信号和第二中间信号之间的差的输出信号。 确定输出信号中的第一预期差分变化，基于第一参考信号中的转变，发生第一预期差分变化。 确定输出信号中的第二个预期差分变化，基于第二参考信号中的转变发生第二预期差分变化。 许多其他操作也在本公开的范围内。