公开(公告)号：US11456300B2

公开(公告)日：2022-09-27

申请号：US17189270

申请日：2021-03-02

申请人： Etron Technology, Inc. ,  Invention And Collaboration Laboratory Pte. Ltd.

发明人： Chao-Chun Lu

IPC分类号： G11C11/24 ,  H01L27/108 ,  G11C5/02 ,  H01L27/06 ,  H01L25/065

摘要： An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

公开(公告)号：US11450380B2

公开(公告)日：2022-09-20

申请号：US16940194

申请日：2020-07-27

申请人： MICRON TECHNOLOGY, INC.

发明人： M. Ataul Karim ,  Timothy M. Hollis

IPC分类号： G11C11/24 ,  G11C11/4093 ,  H04L27/08 ,  G11C11/56

摘要： Apparatuses, systems, and methods for high-pass filtering pre-emphasis circuits. A device may use a pre-emphasis driver to provide a multi-level signal based on multiple binary signals. The pre-emphasis driver includes a primary driver coupled in parallel with at least one equalizer path, each of which includes an equalizer driver and a filtering element. The filtering element may be an AC filtering element, such as a capacitor. The equalizer paths may contribute equalized signal(s) which have a high-pass filtering behavior. The pre-emphasis circuit may combine the primary signal from the primary driver and the equalized signals to generate an overall output multi-level signal. In some embodiments, the pre-emphasis driver may be a pulse amplitude modulated (PAM) driver, such as a PAM4 driver with four levels of the multi-level driver.

公开(公告)号：US11335408B2

公开(公告)日：2022-05-17

申请号：US17200385

申请日：2021-03-12

申请人： Micron Technology, Inc.

发明人： Marco Sforzin ,  Umberto Di Vincenzo

IPC分类号： G11C11/34 ,  G11C16/12 ,  G11C16/28 ,  G11C7/14 ,  G11C11/24 ,  G11C7/06 ,  G11C11/404 ,  G11C13/00 ,  G11C11/56

摘要： A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

公开(公告)号：US11264079B1

公开(公告)日：2022-03-01

申请号：US17127654

申请日：2020-12-18

申请人： MICRON TECHNOLOGY, INC.

发明人： David A. Roberts

IPC分类号： G11C11/24 ,  G11C11/4078

摘要： Apparatuses, systems, and methods for row hammer based cache lockdown. A controller of a memory may include an aggressor detector circuit which determines if addresses are aggressor addresses or not. The controller may include a tracker circuit which may count a number of times an address is identified as an aggressor, and may determine if the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, a cache entry associated with the frequent aggressor address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker which may determine if the frequent aggressor address is a highly attacked address. An address mapping associated with the highly attacked address may be changed.

公开(公告)号：US20220059152A1

公开(公告)日：2022-02-24

申请号：US17453919

申请日：2021-11-08

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Liang CHEN ,  Cheng GAN ,  Xin WU ,  Wei LIU

IPC分类号： G11C11/24 ,  G11C11/404 ,  H01L27/108 ,  H01L49/02

摘要： In a method for manufacturing a semiconductor device, a doped region is formed in a substrate from a first main surface. An insulating layer is formed over the doped region of the substrate. Contacts are formed in the insulating layer such that the contacts extend into the doped region. A portion of the substrate is removed from a second main surface. A trench, a first conductive line, and a second conductive line are formed from the doped region of the substrate through etching the substrate from the second main surface. The trench extends through the substrate to expose the insulating layer. The first and second conductive lines are spaced apart from each other by the trench. The contacts are positioned along and in contact with the first and second conductive lines. The trench is filled with a dielectric material.

公开(公告)号：US11114449B2

公开(公告)日：2021-09-07

申请号：US16810902

申请日：2020-03-06

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Tamae Moriwaka ,  Yuta Endo

IPC分类号： H01L29/10 ,  H01L27/115 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  H01L29/786 ,  H01L27/06 ,  H01L27/1156 ,  H01L27/11551 ,  H01L29/24 ,  G11C11/408

摘要： [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US11069392B2

公开(公告)日：2021-07-20

申请号：US17099413

申请日：2020-11-16

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  John Eric Linstadt ,  Brent Steven Haukness ,  Kenneth L. Wright ,  Thomas Vogelsang

IPC分类号： G11C11/24 ,  G11C11/403 ,  G11C11/4096 ,  G11C8/08 ,  G11C7/10 ,  G11C7/18 ,  G11C5/02 ,  G11C11/408 ,  G06F12/06 ,  G11C11/406 ,  G11C11/409 ,  G11C11/4097 ,  G11C11/4091

摘要： A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

公开(公告)号：US11069385B1

公开(公告)日：2021-07-20

申请号：US16835797

申请日：2020-03-31

申请人： Micron Technology, inc.

发明人： Jiyun Li ,  Scott J. Derner

IPC分类号： G11C11/24 ,  G11C7/08 ,  G11C11/4091 ,  H01L27/108

摘要： Some embodiments include an integrated assembly having a second deck over a first deck. A first true digit line has first and second segments along the first deck. A first complementary digit line has third and fourth segments along the second deck. The first true digit line is comparatively compared to the first complementary digit line. A second true digit line has a third region along the first deck and a fourth region along the second deck. The third region is adjacent the first segment, and the fourth region is adjacent the third segment. A second complementary digit line has a fifth region along the first deck and has a sixth region along the second deck. The fifth region is adjacent the second segment, and the sixth region is adjacent the fourth segment. The second true digit line is comparatively compared to the second complementary digit line.

公开(公告)号：US11062763B2

公开(公告)日：2021-07-13

申请号：US16379222

申请日：2019-04-09

申请人： Micron Technology, Inc.

发明人： Ferdinando Bedeschi ,  Stefan Frederik Schippers

IPC分类号： G11C11/24 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  H01L27/108 ,  G11C11/56

摘要： Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.

公开(公告)号：US20210202005A1

公开(公告)日：2021-07-01

申请号：US17200385

申请日：2021-03-12

申请人： Micron Technology, Inc.

发明人： Marco Sforzin ,  Umberto Di Vincenzo

IPC分类号： G11C16/12 ,  G11C16/28 ,  G11C7/14 ,  G11C11/24 ,  G11C7/06 ,  G11C11/404

摘要： A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.