利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

1468 records (took 0.035 seconds)

    Power amplifier circuit
    11.
    发明授权
    Power amplifier circuit 有权

    公开(公告)号：US11967934B2

    公开(公告)日：2024-04-23

    申请号：US17319879

    申请日：2021-05-13

    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

    Inventor： Takeshi Kawasaki

    IPC: H03F3/68 ,  H03F1/02 ,  H03F1/22 ,  H03F3/21

    CPC classification number: H03F1/0288 ,  H03F3/211 ,  H03F2203/21131

    Abstract: A power amplifier circuit is a Doherty type. A peak amplifier has a first transistor and a second transistor. A first source terminal is connected to a first constant potential line. A first drain terminal and a second source terminal are connected to a first node. A second drain terminal is connected to a second constant potential line having a higher potential than the first constant potential line. A first control terminal is connected to a first bias voltage application circuit, and an input signal is input to the first control terminal via a first alternating current coupling circuit. A second control terminal is connected to a second bias voltage application circuit and is connected to the first node via a second alternating current coupling circuit. The first node is connected to the first constant potential line via a third alternating current coupling circuit.

    Integrated circuit yield improvement
    15.
    发明授权
    Integrated circuit yield improvement 有权

    公开(公告)号：US11923807B2

    公开(公告)日：2024-03-05

    申请号：US17331436

    申请日：2021-05-26

    Applicant: pSemi Corporation

    Inventor： Parvez H. Daruwalla ,  Yucheng Tong ,  Jonathan James Klaren

    IPC: H03F1/22 ,  G01R31/28 ,  H03F3/195 ,  H03F3/24 ,  H03F3/72

    CPC classification number: H03F1/223 ,  G01R31/2834 ,  H03F3/195 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/261 ,  H03F2200/294 ,  H03F2200/451

    Abstract: Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require IDD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit. Both embodiments mitigate or overcome miscalibration of active circuit current settings resulting from ATE test probe resistance.

    AMPLIFIER WITH BIAS CIRCUIT HAVING REPLICATED TRANSCONDUCTANCE DEVICES
    18.
    发明公开
    AMPLIFIER WITH BIAS CIRCUIT HAVING REPLICATED TRANSCONDUCTANCE DEVICES 审中-公开

    公开(公告)号：US20240022221A1

    公开(公告)日：2024-01-18

    申请号：US18319227

    申请日：2023-05-17

    Applicant: QUALCOMM Incorporated

    Inventor： Zaid ABOUSH ,  Noshir Behli DUBASH ,  Abhijeet PAUL ,  Peter Graeme CLARKE

    IPC: H03F3/24 ,  H03F1/22 ,  H03F1/02

    CPC classification number: H03F3/245 ,  H03F1/223 ,  H03F1/0277 ,  H03F2200/451 ,  H03F2200/294

    Abstract: Devices and techniques for amplifying a signal are disclosed. For instance, an amplifier includes an input node and an output node; a first gain segment including: a first transistor, where a gate of the first transistor is coupled to the input node, a first terminal of the first transistor is coupled to a ground, and a second terminal of the first transistor is coupled to the output node; a second gain segment including: a second transistor, where a gate of the second transistor is coupled to the input node, a first terminal of the second transistor is coupled to the ground, and a second terminal of the second transistor is coupled to the output node, where the first gain segment and the second gain segment are arranged in parallel with respect to the output node; and a bias circuit.

Patent Agency Ranking