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公开(公告)号：US11681617B2
公开(公告)日：2023-06-20
申请号：US17199864
申请日：2021-03-12
Applicant: Arm Limited
Inventor： Alexander Klimov
IPC: G06F12/0802 , G06F21/60 , G06F21/62 , G06F21/64
CPC classification number: G06F12/0802 , G06F21/602 , G06F21/62 , G06F21/64 , G06F2212/60
Abstract: A data processing apparatus includes a requester, a completer and a cache. Data is transferred between the requester and the cache and between the cache and the completer. The cache implements a cache eviction policy. The completer determines an eviction cost associated with evicting the data from the cache and notifies the cache of the eviction cost. The cache eviction policy implemented by the cache is based, at least in part, on the cost of evicting the data from the cache. The eviction cost may be determined, for example, based on properties or usage of a memory system of the completer.
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公开(公告)号：US20230185733A1
公开(公告)日：2023-06-15
申请号：US17995898
申请日：2021-04-09
Applicant: Arm Limited
Inventor： Jason PARKER
IPC: G06F12/14
CPC classification number: G06F12/1441 , G06F12/1483 , G06F12/1408
Abstract: Address translation circuitry translates a target virtual address (VA) specified by a memory access request into a target physical address (PA) associated with a selected physical address space (PAS) selected from among a plurality of PASs. A granule protection data block is loaded from memory comprising at least one granule protection entry (GPE), each GPE corresponding to a respective granule of PAs and specifying granule protection information (GPI) indicating which of the PASs is an allowed PAS. Filtering circuitry determines whether the memory access request should be allowed to access the target PA, based on whether the selected PAS is indicated as an allowed PAS by the GPI in a target granule protection entry (GPE). Integrity checking circuitry performs a data integrity check on the granule protection data block loaded from memory, and signals a fault when the data integrity check fails.
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公开(公告)号：US20230178819A1
公开(公告)日：2023-06-08
申请号：US17541000
申请日：2021-12-02
Applicant: Arm Limited
Inventor： Emre OZER , Remy POTTIER , Jedrzej KUFEL , John Philip BIGGS , James Edward MYERS
IPC: H01M10/48 , G01R31/392
CPC classification number: H01M10/482 , G01R31/392
Abstract: A battery cell monitoring system comprises a flexible substrate able to conform to a surface of a battery cell to be monitored, and a plurality of first-level prediction units integrated onto the flexible substrate, where each first-level prediction unit is positioned at a different location on the flexible substrate to each other first-level prediction unit. Each first-level prediction unit comprises at least one sensor to generate sensor signals indicative of a physical state of the battery cell, and first-level prediction circuitry to generate a predicted battery cell status value in dependence on the sensor signals received from the at least one sensor of that first-level prediction unit. Second-level prediction circuitry is arranged to determine a prediction result in dependence on the predicted battery cell status values generated by the first-level prediction circuitry of each first-level prediction unit, and a communications device is used to output the prediction result at least when the prediction result indicates an occurrence of a critical event.
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公开(公告)号：US20230178538A1
公开(公告)日：2023-06-08
申请号：US18103313
申请日：2023-01-30
Applicant: Arm Limited
Inventor： Rahul Mathur , Xiaoqing Xu , Andy Wangkun Chen , Mudit Bhargava , Brian Tracy Cline , Saurabh Pijuskumar Sinha
IPC: H01L27/02 , G06F30/31 , H01L21/768 , H01L23/535 , H01L25/065 , H01L25/00
CPC classification number: H01L27/0207 , G06F30/31 , H01L21/76898 , H01L23/535 , H01L25/0657 , H01L25/50 , H01L2225/06544
Abstract: According to one implementation of the present disclosure, a method includes fabricating a memory macro unit; forming a through silicon via (TSV); and bonding the TSV at least partially through the fabricated memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.
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公开(公告)号：US20230176983A1
公开(公告)日：2023-06-08
申请号：US17906625
申请日：2021-01-26
Applicant: ARM LIMITED
Inventor： Jason PARKER , Andrew Brookfield SWAINE , Yuval ELAD , Martin WEIDMANN
IPC: G06F12/14 , G06F12/1045 , G06F12/0808
CPC classification number: G06F12/1425 , G06F12/1458 , G06F12/1063 , G06F12/0808
Abstract: Address translation circuitry (16) translates a virtual address specified by a memory access request issued by requester circuitry into a target physical address (PA). Requester-side filtering circuitry (20) performs a granule protection lookup based on the target PA and a selected physical address space (PAS) associated with the memory access request, to determine whether to allow the memory access request to be passed to a cache or interconnect. In the granule protection lookup, the requester-side filtering circuitry obtains granule protection information corresponding to a target granule of physical addresses including the target PA, which indicates at least one allowed PAS associated with the target granule, and blocks the memory access request when the granule protection information indicates that the selected PAS is not an allowed PAS.
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Patent Agency Ranking
公开(公告)号：US11664681B2
公开(公告)日：2023-05-30
申请号：US17364057
申请日：2021-06-30
Applicant: Arm Limited
Inventor： Philex Ming-Yan Fan , Parameshwarappa Anand Kumar Savanth , Sahan Sajeewa Hiniduma Udugama Gamage , Pranay Prabhat , Benoit Labbe , Thanusree Achuthan
CPC classification number: H02J50/001 , H02J50/20 , H02J50/40 , H02M3/07
Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.
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公开(公告)号：US11664086B2
公开(公告)日：2023-05-30
申请号：US17375887
申请日：2021-07-14
Applicant: Arm Limited
Inventor： Yew Keong Chong , Andy Wangkun Chen , Bikas Maiti , Vivek Nautiyal
CPC classification number: G11C29/76 , G11C7/1012 , G11C29/18 , G11C29/785 , G11C2029/1802
Abstract: Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.
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公开(公告)号：US11663125B2
公开(公告)日：2023-05-30
申请号：US15987944
申请日：2018-05-24
Applicant: Arm Limited
Inventor： Varun Subramanian , Emmanuel Manrico III Mendoza
CPC classification number: G06F12/0802 , G06F11/3447 , G06F11/3457 , G06N3/02 , G06N3/04 , G06N3/08 , G06N20/00 , G06F2212/1012 , G06F2212/1028 , G06F2212/452
Abstract: Computer-implemented methods using machine learning are provided for generating an estimated cache performance of a cache configuration. A neural network is trained using, as inputs, a set of memory access parameters generated from a non-cycle-accurate simulation of a data processing system comprising the cache configuration and a cache configuration value, and using, as outputs, cache performance values generated by a cycle-accurate simulation of the data processing system comprising the cache configuration. The trained neural network is then provided with sets of memory access parameters generated from a non-cycle-accurate simulation of a proposed data processing system and a selected cache configuration and generates estimated cache performance values for that selected cache configuration.
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公开(公告)号：US11663034B2
公开(公告)日：2023-05-30
申请号：US16651017
申请日：2018-08-21
Applicant: Arm Limited
Inventor： Matthew James Horsnell , Grigorios Magklis , Richard Roy Grisenthwaite , Stephan Diestelhorst
CPC classification number: G06F9/467 , G06F9/3009 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/466 , G06F9/4812 , G06F11/1402 , G06F11/1474
Abstract: A data processing apparatus has processing circuitry with transactional memory support circuitry to support execution of a transaction using transactional memory. In response to an exception mask updating instruction which updates exception mask information to enable at least one subset of exceptions which was disabled at the start of processing of a transaction, the processing circuitry permits un-aborted processing of one or more subsequent instruction of the transaction that follow the exception mask update instruction.
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公开(公告)号：US11663007B2
公开(公告)日：2023-05-30
申请号：US17492068
申请日：2021-10-01
Applicant: Arm Limited
CPC classification number: G06F9/30065 , G06F9/325 , G06F9/3846
Abstract: In response to decoding a zero-overhead loop control instruction of an instruction set architecture, processing circuitry sets at least one loop control parameter for controlling execution of one or more iterations of a program loop body of a zero-overhead loop. Based on the at least one loop control parameter, loop control circuitry controls execution of the one or more iterations of the program loop body of the zero-overhead loop, the program loop body excluding the zero-overhead loop control instruction. Branch prediction disabling circuitry detects whether the processing circuitry is executing the program loop body of the zero-overhead loop associated with the zero-overhead loop control instruction, and dependent on detecting that the processing circuitry is executing the program loop body of the zero-overhead loop, disables branch prediction circuitry. This reduces power consumption during a zero-overhead loop when the branch prediction circuitry is unlikely to provide a benefit.
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