公开(公告)号：US11023411B2

公开(公告)日：2021-06-01

申请号：US16541070

申请日：2019-08-14

Applicant: XILINX, INC.

Inventor： Steven L. Pope ,  David J. Riddoch ,  Dmitri Kitariev

IPC: H04L12/26 ,  G06F15/173 ,  G06F13/38 ,  G06F3/06 ,  G06F13/28 ,  H04L29/08 ,  G06F9/455 ,  H04L12/861

Abstract: A data processing system and method are provided. A host computing device comprises at least one processor. A network interface device is arranged to couple the host computing device to a network. The network interface device comprises a buffer for receiving data for transmission from the host computing device. The processor is configured to execute instructions to transfer the data for transmission to the buffer. The data processing system further comprises an indicator store configured to store an indication that at least some of the data for transmission has been transferred to the buffer wherein the indication is associated with a descriptor pointing to the buffer.

公开(公告)号：US11017822B1

公开(公告)日：2021-05-25

申请号：US16672089

申请日：2019-11-01

Applicant: XILINX, INC.

Inventor： Sree Rkc Saraswatula ,  Narendra Kumar Pulipati ,  Santosh Yachareni ,  Shidong Zhou ,  Sundeep Ram Gopal Agarwal ,  Brian Gaide

IPC: G11C5/14 ,  G11C29/50 ,  H01L25/065

Abstract: Examples described herein provide a method for disabling a defective portion of a fabric die of a stacked IC device. The method includes receiving a signal indicating that a portion of a fabric die of a stacked IC device including at least two fabric dies is defective. The method further includes, in response to the signal, pulling a source voltage rail of the defective portion to ground, thereby disabling the portion, and operating the remainder of the fabric die without interference from or contention with the disabled portion. In one example, the stacked IC device is an active on active (AoA) device, and the portion of the fabric die includes a configuration memory cell. In one example, the signal is received after power-up of the stacked IC device.

公开(公告)号：US20210152180A1

公开(公告)日：2021-05-20

申请号：US16688130

申请日：2019-11-19

Applicant: Xilinx, Inc.

Inventor： Jaewook Shin ,  Parag Upadhyaya ,  Shaojun MA

IPC: H03L7/24 ,  H03K3/03 ,  H03L7/099 ,  H03L7/083 ,  H03B5/12 ,  H04L7/033 ,  G06F1/08

Abstract: A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.

公开(公告)号：US11003818B1

公开(公告)日：2021-05-11

申请号：US16790578

申请日：2020-02-13

Applicant: Xilinx, Inc.

Inventor： Ashish Kumar Jain ,  Saikat Bandyopadhyay ,  Jason Villarreal

IPC: G06F30/00 ,  G06F30/33 ,  G06F9/30 ,  G06F30/3308 ,  G06F7/499

Abstract: A method includes parsing and compiling a software code that includes a constraint bitwise operation with a first operand associated with a first constraint range and a second operand associated with a second constraint range. A first and a second plurality of ranges that spans the first and second constraint range are generated. In some embodiments, each constrained range is converted into a binary format having an upper bit portion and a lower bit portion. The upper bit portion for the each range remains unchanged. A resultant range associated with the constraint bitwise operation is determined based on performing the constraint bitwise operation on the first and the second plurality of ranges.

公开(公告)号：US11003204B1

公开(公告)日：2021-05-11

申请号：US16216990

申请日：2018-12-11

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  Edward Cullen ,  Brendan Farley

IPC: G06F1/08 ,  G06F1/324 ,  H03K3/0231 ,  H03K3/011 ,  G06F1/3296 ,  H03B5/12 ,  H03L7/099

Abstract: Examples described herein provide for a relaxation oscillator and corresponding methods of operation. In an example, a circuit includes a dynamically controllable current source, a capacitor, and an oscillator generation circuit. The dynamically controllable current source includes a digitally tunable current mirror configured to generate a current. The digitally tunable current mirror includes multiple transistors configured to be selectively electrically connected in parallel to alter a gain of the digitally tunable current mirror to control the current. The capacitor is selectively electrically connected to the dynamically controllable current source. The oscillator generation circuit is electrically connected to the capacitor. The oscillator generation circuit is configured to generate an oscillation signal in response to a voltage of the capacitor.

公开(公告)号：US10999246B2

公开(公告)日：2021-05-04

申请号：US16121366

申请日：2018-09-04

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  Derek Edward Roberts ,  David James Riddoch

IPC: G06F21/00 ,  H04L29/06 ,  G06Q40/04

Abstract: A logic device and method are provided for intercepting a data flow from a network source to a network destination. A data store holds a set of compliance rules and corresponding actions. A packet inspector is configured to inspect the intercepted data flow and identify from the data store a compliance rule associated with the inspected data flow. A packet filter is configured to, when the data flow is identified as being associated with a compliance rule, carry out an action with respect to the data flow corresponding to the compliance rule.

公开(公告)号：US10998904B1

公开(公告)日：2021-05-04

申请号：US16686073

申请日：2019-11-15

Applicant: Xilinx, Inc.

Inventor： Sundeep Ram Gopal Agarwal ,  Brian C. Gaide ,  Ramakrishna Kishore Tanikella

IPC: H03K19/00 ,  H01L25/065

Abstract: Configurable termination circuits for use with programmable logic devices are disclosed. In one implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to a fixed voltage. In another implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to an output of the one or more configurable logic blocks. In some implementations, the programmable logic device may include a platform management controller to configure the termination circuits based on configuration data.

公开(公告)号：US10990517B1

公开(公告)日：2021-04-27

申请号：US16259895

申请日：2019-01-28

Applicant: Xilinx, Inc.

Inventor： Hare K. Verma ,  Jiayou Wang ,  Vincent Mirian

IPC: G06F12/02

Abstract: Examples described herein relate to efficient memory access. An example is a system includes a programmable device, and a memory. The programmable device is coupled to the host and receives the read/write requests and the addresses associated therewith. The programmable device interleaves the read/write requests across multiple communication channels based on a subset of bits within each address. The memory receives the read/write requests from the programmable device. The memory stores contents associated with the addresses for write requests and returns contents associated with the addresses for a read request to the programmable device. The programmable device returns the received contents to the host for processing.

公开(公告)号：US20210119317A1

公开(公告)日：2021-04-22

申请号：US17051854

申请日：2019-05-02

Applicant: XILINX, INC.

Inventor： Peter MEYER

IPC: H01Q1/12 ,  H01Q1/24 ,  H05K7/20 ,  H01Q1/02

Abstract: The present invention provides an antenna system (100, 200, 211, 300, 400, 500, 600) for attachment to an antenna pole (250, 350), the antenna system (100, 200, 211, 300, 400, 500, 600) comprising a cooling arrangement (101, 201, 212, 301, 401, 501, 601), an active electronic arrangement (102, 202, 213, 302, 402, 502, 602) that comprises a number of antenna elements (103, 104) and a number of receivers and/or transmitters for the antenna elements (103, 104), wherein the active electronic arrangement (102, 202, 213, 302, 402, 502, 602) is releasably attachable to the cooling arrangement (101, 201, 212, 301, 401, 501, 601). Further, the present invention provides a communication system (210) and a method for manufacturing an antenna system (100, 200, 211, 300, 400, 500, 600).

公开(公告)号：US10977401B1

公开(公告)日：2021-04-13

申请号：US16724553

申请日：2019-12-23

Applicant: Xilinx, Inc.

Inventor： Jeffrey M. Arnold ,  Stephen L. Bade ,  Srinivas Beeravolu ,  Chukwuweta Chukwudebe ,  Anindita Patra ,  Nabeel Shirazi

IPC: G06F30/327 ,  G06F30/343 ,  G06F30/398

Abstract: Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.