公开(公告)号：US08013711B2

公开(公告)日：2011-09-06

申请号：US12280013

申请日：2007-02-27

Applicant: Zhiqiang Wei ,  Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima

Inventor： Zhiqiang Wei ,  Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima

IPC: H01C7/10

CPC classification number: H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1683 ,  Y10T29/49099

Abstract: A method for manufacturing a variable resistance element includes the steps of: depositing a variable resistance material (106) in a contact hole (105), which is formed on an interlayer insulating layer (104) on a substrate and has a lower electrode (103) at a bottom portion thereof, such that an upper surface of the variable resistance material (106) in the contact hole (105) is located lower than an upper surface of the interlayer insulating layer (104); depositing an upper electrode material on the deposited variable resistance material (106) such that an upper surface of the upper electrode material in the contact hole (105) is located higher than the upper surface of the interlayer insulating layer (104); and element-isolating by a CMP the variable resistance element including the variable resistance material (106) and the upper electrode material.

Abstract translation: 一种制造可变电阻元件的方法包括以下步骤：将可变电阻材料（106）沉积在形成在衬底上的层间绝缘层（104）上的接触孔（105）中，并具有下电极（103） ），使得所述接触孔（105）中的所述可变电阻材料（106）的上表面位于所述层间绝缘层（104）的上表面以下。 在所述沉积的可变电阻材料（106）上沉积上电极材料，使得所述接触孔（105）中的上电极材料的上表面位于比所述层间绝缘层（104）的上表面高; 以及通过CMP对包括可变电阻材料（106）和上电极材料的可变电阻元件进行元件隔离。

公开(公告)号：US20110128776A1

公开(公告)日：2011-06-02

申请号：US13056925

申请日：2010-05-14

Applicant: Yoshikazu Katoh ,  Shunsaku Muraoka ,  Takeshi Takagi

Inventor： Yoshikazu Katoh ,  Shunsaku Muraoka ,  Takeshi Takagi

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/0069 ,  G11C11/14 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0038 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/34 ,  G11C2213/79 ,  G11C2213/82

Abstract: A resistance variable layer has a characteristic in which the resistance variable layer changes to a second resistance state (RL) in such a manner that its resistance value stops decreasing when an interelectrode voltage reaches a first voltage (V1) which is a negative voltage, the resistance variable layer changes to a first resistance state (RH) in such a manner that its resistance value starts increasing when the interelectrode voltage reaches a second voltage (V2) which is a positive voltage which is equal in absolute value to the first voltage, the resistance variable layer changes to the first resistance state in such a manner that the resistance variable layer flows an interelectrode current such that the interelectrode voltage is maintained at a third voltage (V3) higher than the second voltage, when the interelectrode voltage reaches the third voltage, and the resistance variable layer changes to the first resistance state in such a manner that its resistance value stops increasing when the interelectrode current reaches a first current (Ilim) in a state where the interelectrode voltage is not lower than the second voltage and lower than the third voltage, and the load resistor has a characteristic in which when the electric pulse application device outputs an electric pulse of a second application voltage (VP2), a current flowing by applying to the load resistor, a voltage obtained by subtracting the third voltage from the second application voltage, is not higher than a first current value.

Abstract translation: 电阻变化层具有电阻变化层变为第二电阻状态（RL）的特性，使得当电极间电压达到作为负电压的第一电压（V1）时，其电阻值停止减小， 电阻变化层以这样的方式改变为第一电阻状态（RH），使得当电极间电压达到作为与第一电压的绝对值相等的正电压的第二电压（V2）时，其电阻值开始增加， 电阻变化层以这样的方式变化为电阻变化层流动电极间电流，使得当电极间电压达到第三电压时，电极间电压保持在高于第二电压的第三电压（V3） ，并且电阻变化层以其电阻值停止增加的方式变为第一电阻状态 当所述电极间电流在所述电极间电压不低于所述第二电压且低于所述第三电压的状态下达到第一电流（Ilim）时，并且所述负载电阻器具有当所述电脉冲施加装置输出 第二施加电压（VP2）的电脉冲，通过施加到负载电阻器流动的电流，从第二施加电压减去第三电压获得的电压不高于第一电流值。

公开(公告)号：US20110110143A1

公开(公告)日：2011-05-12

申请号：US13001840

申请日：2010-04-09

Applicant: Yoshihiko Kanzawa ,  Takeshi Takagi

Inventor： Yoshihiko Kanzawa ,  Takeshi Takagi

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/0011 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/34 ,  G11C2213/79

Abstract: Provided is a programming method for improving the retention characteristics of information in a variable resistance nonvolatile memory element. The method includes: a first writing process of applying a first voltage V1 having a first polarity to set the variable resistance nonvolatile storage element to a low resistance state LR indicating first logic information (S01); a second writing process of applying a second voltage V2 having a second polarity different from the first polarity to set the variable resistance nonvolatile storage element to a first high resistance state HR1 (S02); and a partial write process of applying a third voltage V3 having the first polarity so as to set the variable resistance layer to a second high resistance state HR2 indicating second logic information different from the first logic information (S05). Here, |V3|

Abstract translation: 提供了一种用于改善可变电阻非易失性存储元件中的信息的保持特性的编程方法。 该方法包括：施加具有第一极性的第一电压V1的第一写入处理将可变电阻非易失性存储元件设置为指示第一逻辑信息的低电阻状态LR（S01）; 第二写入处理，施加具有与第一极性不同的第二极性的第二电压V2，以将可变电阻非易失性存储元件设置为第一高电阻状态HR1（S02）; 以及施加具有第一极性的第三电压V3以便将可变电阻层设置为指示与第一逻辑信息不同的第二逻辑信息的第二高电阻状态HR2的部分写入处理（S05）。 这里，| V3 | <| V1 |，HR1，HR2，LR中的电阻值依次较大。

公开(公告)号：US07919774B2

公开(公告)日：2011-04-05

申请号：US12709148

申请日：2010-02-19

Applicant: Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

Inventor： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

IPC: H01L29/68 ,  H01L21/34

CPC classification number: H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1658 ,  H01L45/1675

Abstract: A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

Abstract translation: 设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。 金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及 具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。

公开(公告)号：US20110007553A1

公开(公告)日：2011-01-13

申请号：US12865193

申请日：2009-10-16

Applicant: Takeshi Takagi ,  Shunsaku Muraoka ,  Mitsuteru Iijima ,  Ken Kawai ,  Kazuhiko Shimakawa

Inventor： Takeshi Takagi ,  Shunsaku Muraoka ,  Mitsuteru Iijima ,  Ken Kawai ,  Kazuhiko Shimakawa

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/79

Abstract: Provided is a nonvolatile storage device (200) capable of stably operating without increasing a size of a selection transistor included in each of memory cells. The nonvolatile storage device (200) includes: a semiconductor substrate (301) which has a P-type well (301a) of a first conductivity type; a memory cell array (202) which includes memory cells (M11) or the like each of which includes a variable resistance element (R11) and a transistor (N11) that are formed above the semiconductor substrate (301) and connected in series; and a substrate bias circuit (220) which applies, to the P-type well (301a), a bias voltage in a forward direction with respect to a source and a drain of the transistor (N11), when a voltage pulse for writing is applied to the variable resistance element (R11) included in the selected memory cell (M11) or the like.

Abstract translation: 提供一种能够在不增加包含在每个存储单元中的选择晶体管的尺寸的情况下稳定地工作的非易失性存储装置（200）。 非易失性存储装置（200）包括：具有第一导电型的P型阱（301a）的半导体基板（301） 存储单元阵列（202），其包括存储单元（M11）等，每个存储单元包括形成在半导体衬底（301）上并串联连接的可变电阻元件（R11）和晶体管（N11）; 以及衬底偏置电路（220），当用于写入的电压脉冲为写入电压脉冲时，向P型阱（301a）施加相对于晶体管（N11）的源极和漏极的正向偏置电压 应用于所选择的存储单元（M11）等中包含的可变电阻元件（R11）。

公开(公告)号：US20110002158A1

公开(公告)日：2011-01-06

申请号：US12918874

申请日：2009-02-25

Applicant: Shunsaku Muraoka ,  Takeshi Takagi ,  Kazuhiko Shimakawa

Inventor： Shunsaku Muraoka ,  Takeshi Takagi ,  Kazuhiko Shimakawa

IPC: G11C11/00

CPC classification number: H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/009 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: A method of programming a variable resistance element to be operated with stability and at a high speed is provided. The method programs a nonvolatile variable resistance element (10) including a variable resistance layer (3), which changes between a high resistance state and a low resistance state depending on a polarity of an applied electric pulse, and a lower electrode (2) and an upper electrode (4). The method includes: writing steps (S11) and (S15) to cause the variable resistance layer (3) to change from the low resistance state to the high resistance state by applying a write voltage pulse; and an erasing step (S13) to cause the variable resistance layer (3) to change from the high resistance state to the low resistance state. In the writing steps, a write voltage pulse is applied between the electrodes so as to satisfy |Vw1|>|Vw| where Vw1 represents a voltage value of the write voltage pulse in the first writing step (S11) after manufacturing the variable resistance element (10) and Vw represents a voltage value of the write voltage pulse in writing steps after the first writing step (S15) after manufacturing the variable resistance element (10).

Abstract translation: 提供了一种以稳定且高速度操作的可变电阻元件的编程方法。 该方法编程包括可变电阻层（3）的非易失性可变电阻元件（10），其根据所施加的电脉冲的极性在高电阻状态和低电阻状态之间变化;以及下电极（2）和 上电极（4）。 该方法包括：写入步骤（S11）和（S15），通过施加写入电压脉冲使可变电阻层（3）从低电阻状态变为高电阻状态; 以及使可变电阻层（3）从高电阻状态变为低电阻状态的擦除步骤（S13）。 在写入步骤中，在电极之间施加写入电压脉冲，以满足| Vw1 |> | Vw | 其中Vw1表示制造可变电阻元件（10）之后的第一写入步骤（S11）中的写入电压脉冲的电压值，Vw表示在第一写入步骤之后的写入步骤中的写入电压脉冲的电压值（S15） 在制造可变电阻元件（10）之后。

公开(公告)号：US20110001109A1

公开(公告)日：2011-01-06

申请号：US12920154

申请日：2010-02-03

Applicant: Takeki Ninomiya ,  Takeshi Takagi ,  Zhiqiang Wei

Inventor： Takeki Ninomiya ,  Takeshi Takagi ,  Zhiqiang Wei

IPC: H01L45/00

CPC classification number: H01L45/146 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1625 ,  H01L45/1675

Abstract: A nonvolatile memory element (100) includes a variable resistance layer (107) including a first metal oxide MOx and a second metal oxide MOy, and reaction energy of chemical reaction related to the first metal oxide, the second metal oxide, oxygen ions, and electrons is 2 eV or less. The chemical reaction is expressed by a formula 13, where a combination (MOx, MOy) of MOx and MOy is selected from a group including (Cr2O3, CrO3), (Co3O4, Co2O3), (Mn3O4, Mn2O3), (VO2, V2O5), (Ce2O3, CeO2), (W3O8, WO3), (Cu2O, CuO), (SnO, SnO2), (NbO2, Nb2O5), and (Ti2O3, TiO2). [Mathematical Expression 13] MOX+(y−x)O2−MOy+2(y−x)e−  (Formula 13)

Abstract translation: 非易失性存储元件（100）包括可变电阻层（107），其包括第一金属氧化物MOx和第二金属氧化物MOy，以及与第一金属氧化物，第二金属氧化物，氧离子和 电子为2eV以下。 化学反应由式13表示，其中MOx和MOy的组合（MOx，MOy）选自（Cr 2 O 3，CrO 3），（Co 3 O 4，Co 2 O 3），（Mn 3 O 4，Mn 2 O 3），（VO 2，V 2 O 5） ），（Ce 2 O 3，CeO 2），（W3O 8，WO 3），（Cu 2 O，CuO），（SnO，SnO 2），（NbO 2，Nb 2 O 5）和（Ti 2 O 3，TiO 2）。 [数学表达式13] MOX +（y-x）O 2 -Moy + 2（y-x）e-（式13）

公开(公告)号：US20100225438A1

公开(公告)日：2010-09-09

申请号：US12280013

申请日：2007-02-27

Applicant: Zhiqiang Wei ,  Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima

Inventor： Zhiqiang Wei ,  Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima

IPC: H01C7/10 ,  H01C17/06

CPC classification number: H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1683 ,  Y10T29/49099

Abstract: A method for manufacturing a variable resistance element includes the steps of: depositing a variable resistance material (106) in a contact hole (105), which is formed on an interlayer insulating layer (104) on a substrate and has a lower electrode (103) at a bottom portion thereof, such that an upper surface of the variable resistance material (106) in the contact hole (105) is located lower than an upper surface of the interlayer insulating layer (104); depositing an upper electrode material on the deposited variable resistance material (106) such that an upper surface of the upper electrode material in the contact hole (105) is located higher than the upper surface of the interlayer insulating layer (104); and element-isolating by a CMP the variable resistance element including the variable resistance material (106) and the upper electrode material.

Abstract translation: 一种制造可变电阻元件的方法包括以下步骤：将可变电阻材料（106）沉积在形成在衬底上的层间绝缘层（104）上的接触孔（105）中，并具有下电极（103） ），使得所述接触孔（105）中的所述可变电阻材料（106）的上表面位于所述层间绝缘层（104）的上表面以下。 在所述沉积的可变电阻材料（106）上沉积上电极材料，使得所述接触孔（105）中的上电极材料的上表面位于比所述层间绝缘层（104）的上表面高; 以及通过CMP对包括可变电阻材料（106）和上电极材料的可变电阻元件进行元件隔离。

公开(公告)号：US20100065807A1

公开(公告)日：2010-03-18

申请号：US12513638

申请日：2007-11-16

Applicant: Takeshi Takagi ,  Takumi Mikawa

Inventor： Takeshi Takagi ,  Takumi Mikawa

IPC: H01L27/10 ,  H01L21/02

CPC classification number: H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

Abstract: The present invention is configured such that a resistance variable element (16) and a rectifying element (20) are formed on a substrate (12). The resistance variable element (16) is configured such that a resistance variable layer (14) made of a metal oxide material is sandwiched between a lower electrode (13) and an upper electrode (15). The rectifying element (20) is connected to the resistance variable element (16), and is configured such that a blocking layer (18) is sandwiched between a first electrode layer (17) located on a lower side of the blocking layer (18) and a second electrode layer (19) located on an upper side of the blocking layer (18). The resistance variable element (16) and the rectifying element (20) are connected to each other in series in a thickness direction of the resistance variable layer (14), and the blocking layer (18) is formed as a barrier layer having a hydrogen barrier property.

Abstract translation: 本发明被构造成使得在基板（12）上形成电阻可变元件（16）和整流元件（20）。 电阻可变元件（16）被构造为使得由金属氧化物材料制成的电阻变化层（14）夹在下电极（13）和上电极（15）之间。 整流元件（20）连接到电阻可变元件（16），并且被构造为使阻挡层（18）夹在位于阻挡层（18）的下侧的第一电极层（17）之间， 以及位于阻挡层（18）的上侧的第二电极层（19）。 电阻可变元件（16）和整流元件（20）在电阻变化层（14）的厚度方向上串联连接，并且阻挡层（18）形成为具有氢的阻挡层 屏障属性。

公开(公告)号：US20100014343A1

公开(公告)日：2010-01-21

申请号：US12529466

申请日：2008-10-28

Applicant: Zhiqiang Wei ,  Takeshi Takagi ,  Ken Kawai ,  Kazuhiko Shimakawa

Inventor： Zhiqiang Wei ,  Takeshi Takagi ,  Ken Kawai ,  Kazuhiko Shimakawa

IPC: G11C11/00 ,  G11C11/416

CPC classification number: H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2211/5646 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

Abstract: [Objective] A nonvolatile memory apparatus and a nonvolatile data storage medium of the present invention, including nonvolatile memory elements each of which changes its resistance in response to electric pulses applied, comprises a first write circuit (106) for performing first write in which a first electric pulse is applied to the nonvolatile memory element to switch a resistance value of the nonvolatile memory element from a first resistance value to a second resistance value and a second electric pulse which is opposite in polarity to the first electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the second resistance value to the first resistance value; and a second write circuit (108) for performing second write in which a third electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from a third resistance value to a fourth resistance value and a fourth electric pulse which is identical in polarity to the third electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the fourth resistance value to a fifth resistance value.

Abstract translation: [目的]本发明的非易失性存储装置和非易失性数据存储介质，包括响应于施加的电脉冲改变其电阻的非易失性存储元件，包括用于执行第一写入的第一写入电路（106），其中 将第一电脉冲施加到非易失性存储元件，以将非易失性存储元件的电阻值从第一电阻值切换到第二电阻值，并将与第一电脉冲极性相反的第二电脉冲施加到非易失性存储元件 存储元件，用于将非易失性存储元件的电阻值从第二电阻值切换到第一电阻值; 以及第二写入电路（108），用于执行第二写入，其中第三电脉冲被施加到非易失性存储元件，以将非易失性存储元件的电阻值从第三电阻值切换到第四电阻值和第四电脉冲 将与第三电脉冲相同的极性相加到非易失性存储元件，以将非易失性存储元件的电阻值从第四电阻值切换到第五电阻值。