公开(公告)号：US08796660B2

公开(公告)日：2014-08-05

申请号：US12375881

申请日：2007-09-21

申请人： Takeshi Takagi ,  Takumi Mikawa

发明人： Takeshi Takagi ,  Takumi Mikawa

IPC分类号： H01L29/02 ,  H01L47/00 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L31/0352 ,  H01L45/00 ,  H01L27/24 ,  H01L27/10 ,  H01L21/00 ,  G11C11/00

CPC分类号： H01L45/04 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1683

摘要： A nonvolatile memory element (20) of the present invention comprises a resistance variable element (14) and a diode (18) which are formed on a substrate (10) such that the resistance variable element (14) has a resistance variable layer (11) sandwiched between a lower electrode (12) and an upper electrode (13), and the diode (18) which is connected in series with the resistance variable element (14) in the laminating direction and has an insulating layer or semiconductor layer (15) sandwiched between a first electrode (16) at the lower side and a second electrode (17) at the upper side. The resistance variable layer (11) is embedded in a first contact hole (21) formed on the lower electrode (12). A first area (22) where insulating layer or semiconductor layer (15) of the diode (18) is in contact with a first electrode (16) of the diode (18) is larger than at least one of a second area (23) where the resistance variable layer (11) is in contact with the upper electrode (13) and a third area (24) where the resistance variable layer (11) is in contact with the lower electrode (12).

摘要翻译： 本发明的非易失性存储元件（20）包括形成在基板（10）上的电阻可变元件（14）和二极管（18），使得电阻可变元件（14）具有电阻变化层（11 ）和位于下电极（12）和上电极（13）之间的二极管（18），以及与电阻可变元件（14）在层叠方向上串联连接并具有绝缘层或半导体层（15）的二极管 ）夹在下侧的第一电极（16）和上侧的第二电极（17）之间。 电阻变化层（11）嵌入形成在下电极（12）上的第一接触孔（21）中。 二极管（18）的绝缘层或半导体层（15）与二极管（18）的第一电极（16）接触的第一区域（22）大于第二区域（23）中的至少一个， 其中电阻变化层（11）与上电极（13）接触，电阻变化层（11）与下电极（12）接触的第三区域（24）。

公开(公告)号：US08258493B2

公开(公告)日：2012-09-04

申请号：US12515379

申请日：2007-11-13

申请人： Takumi Mikawa ,  Takeshi Takagi

发明人： Takumi Mikawa ,  Takeshi Takagi

IPC分类号： H01L29/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

摘要： A nonvolatile semiconductor memory apparatus (10) of the present invention comprises a substrate (10), lower-layer electrode wires (15) provided on the substrate (11), an interlayer insulating layer (16) which is disposed on the substrate (11) including the lower-layer electrode wires (15) and is provided with contact holes at locations respectively opposite to the lower-layer electrode wires (15), resistance variable layers (18) which are respectively connected to the lower-layer electrode wires (15); and non-ohmic devices (20) which are respectively provided on the resistance variable layers (18) such that the non-ohmic devices are respectively connected to the resistance variable layers (18). The non-ohmic devices (20) each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer (16).

摘要翻译： 本发明的非易失性半导体存储装置（10）具备基板（10），设置在基板（11）上的下层电极布线（15），设置在基板（11）上的层间绝缘层（16） ），并且在分别与下层电极线（15）相对的位置设置接触孔，电阻变化层（18）分别与下层电极线（15）连接 15）; 和非欧姆器件（20），其分别设置在电阻变化层（18）上，使得非欧姆器件分别连接到电阻变化层（18）。 非欧姆装置（20）各自具有包括多个半导体层的层叠层结构，包括金属电极层和绝缘体层的层叠层结构，或者包括金属电极层和半导体层的层叠层结构 。 嵌入层叠层结构的一层以填充每个接触孔，作为层叠层结构的另一层的半导体层或绝缘体层的面积比每个接触孔的开口大， 设置在层间绝缘层（16）上。

公开(公告)号：US08093578B2

公开(公告)日：2012-01-10

申请号：US12513638

申请日：2007-11-16

申请人： Takeshi Takagi ,  Takumi Mikawa

发明人： Takeshi Takagi ,  Takumi Mikawa

IPC分类号： H01L27/10 ,  H01L21/02

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

摘要： The present invention is configured such that a resistance variable element (16) and a rectifying element (20) are formed on a substrate (12). The resistance variable element (16) is configured such that a resistance variable layer (14) made of a metal oxide material is sandwiched between a lower electrode (13) and an upper electrode (15). The rectifying element (20) is connected to the resistance variable element (16), and is configured such that a blocking layer (18) is sandwiched between a first electrode layer (17) located on a lower side of the blocking layer (18) and a second electrode layer (19) located on an upper side of the blocking layer (18). The resistance variable element (16) and the rectifying element (20) are connected to each other in series in a thickness direction of the resistance variable layer (14), and the blocking layer (18) is formed as a barrier layer having a hydrogen barrier property.

摘要翻译： 本发明被构造成使得在基板（12）上形成电阻可变元件（16）和整流元件（20）。 电阻可变元件（16）被构造为使得由金属氧化物材料制成的电阻变化层（14）夹在下电极（13）和上电极（15）之间。 整流元件（20）连接到电阻可变元件（16），并且被构造为使阻挡层（18）夹在位于阻挡层（18）的下侧的第一电极层（17）之间， 以及位于阻挡层（18）的上侧的第二电极层（19）。 电阻可变元件（16）和整流元件（20）在电阻变化层（14）的厚度方向上串联连接，并且阻挡层（18）形成为具有氢的阻挡层 屏障属性。

公开(公告)号：US20090014710A1

公开(公告)日：2009-01-15

申请号：US12281034

申请日：2007-03-06

申请人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

发明人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

IPC分类号： H01L45/00

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1658 ,  H01L45/1675

摘要： A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

摘要翻译： 设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。 金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及 具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。

公开(公告)号：US08559205B2

公开(公告)日：2013-10-15

申请号：US13563321

申请日：2012-07-31

申请人： Takumi Mikawa ,  Takeshi Takagi

发明人： Takumi Mikawa ,  Takeshi Takagi

IPC分类号： G11C17/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

摘要： A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer.

摘要翻译： 一种非易失性半导体存储装置，包括基板，设置在基板上的下层电极布线，在与下层电极布线分别相对的位置设置有接触孔的层间绝缘层，分别与下层电极布线连接的电阻变化层， 层电极线; 以及分别设置在电阻变化层上的非欧姆器件。 非欧姆性器件各自具有包括多个半导体层的层压层结构，包括金属电极层和绝缘体层的层叠层结构，或者包括金属电极层和半导体层的层叠结构。 嵌入层叠层结构的一层以填充每个接触孔，作为层叠层结构的另一层的半导体层或绝缘体层的面积比每个接触孔的开口大， 设置在层间绝缘层上。

公开(公告)号：US08295123B2

公开(公告)日：2012-10-23

申请号：US12669174

申请日：2008-07-11

申请人： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

发明人： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

IPC分类号： G11C13/00

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L45/00

摘要： In a current rectifying element (10), a barrier height φA of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height φB of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1

摘要翻译： 在电流整流元件（10）中，阻挡层（11）在其厚度方向上的中心区域（14）的阻挡高度＆amp; A被夹在第一电极层（12）和第二电极层（13）之间 ）形成为大于阻挡层（11）和第一电极层（12）之间的界面（17）附近的区域和阻挡层（17）之间的界面（17）的势垒高度B （11）和第二电极层（13）。 阻挡层（11）具有例如阻挡层（11a），（11b）和（11c）的三层结构。 阻挡层（11a），（11b）和（11c）例如由SiNx2，SiNx1和SiNx1（X1

公开(公告)号：US07981760B2

公开(公告)日：2011-07-19

申请号：US12669812

申请日：2009-05-07

申请人： Yoshio Kawashima ,  Takumi Mikawa ,  Takeshi Takagi ,  Koji Arita

发明人： Yoshio Kawashima ,  Takumi Mikawa ,  Takeshi Takagi ,  Koji Arita

IPC分类号： H01L21/00

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

摘要： A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.

摘要翻译： 一种用于制造使上部电极和下部电极之间的形状偏移最小化的非易失性存储元件的方法，包括：依次沉积导电的连接电极层，下部电极层和可变电阻层 的非贵金属氮化物，并且是导电的，由贵金属制成的上电极层和掩模层; 将掩模层形成为预定形状; 通过使用掩模层作为掩模通过蚀刻将上电极层，可变电阻层和下电极层形成为预定形状; 并且同时去除已经通过蚀刻暴露的掩模和连接电极层的区域。

公开(公告)号：US07960770B2

公开(公告)日：2011-06-14

申请号：US12445380

申请日：2007-10-12

申请人： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

发明人： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

IPC分类号： H01L29/76

CPC分类号： H01L27/101 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1683

摘要： A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).

摘要翻译： 下电极（22）设置在半导体芯片基板（26）上。 下部电极（22）从上方被第一层间绝缘层（27）覆盖。 第一接触孔（28）设置在下电极（22）上以穿透第一层间绝缘层（27）。 嵌入形成电阻变化层（24）的低电阻层（29），以填充第一接触孔（28）。 在第一层间绝缘层（27）和低电阻层（29）上设置有高电阻层（30）。 电阻变化层（24）由包含单层高电阻层（30）和单层低电阻层（29）的多层电阻层形成。 形成存储器部分（25）的低电阻层（29）至少与其相邻的存储器部分（25）隔离。

公开(公告)号：US07915656B2

公开(公告)日：2011-03-29

申请号：US12446964

申请日：2007-10-22

申请人： Takumi Mikawa ,  Takeshi Takagi

发明人： Takumi Mikawa ,  Takeshi Takagi

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/20

CPC分类号： H01L27/101 ,  H01L27/24

摘要： A nonvolatile semiconductor memory apparatus (10) of the present invention comprises a semiconductor substrate (11), an active element forming region provided on the semiconductor substrate (11) and including a plurality of active elements (12), a wire forming region which is provided on the active element forming region to electrically connect the active elements (12) and includes plural layers of semiconductor electrode wires (15, 16), a memory portion forming region (100) which is provided above the wire forming region and provided with memory portions (26) arranged in matrix, a resistance value of each of the memory portions changing according to electric pulses applied, and an oxygen barrier layer (17) which is provided between the memory portion forming region (100) and the wire forming region so as to extend continuously over at least an entire of the memory portion forming region (100).

摘要翻译： 本发明的非易失性半导体存储器件（10）包括半导体衬底（11），设置在半导体衬底（11）上并包括多个有源元件（12）的有源元件形成区域， 设置在有源元件形成区域上以电连接有源元件（12）并且包括多层半导体电极线（15,16），存储部形成区域（100），其设置在线形成区域的上方并设置有存储器 布置成矩阵的部分（26），每个存储部分的电阻值根据施加的电脉冲而变化，以及设置在存储部分形成区域（100）和线形成区域之间的氧阻挡层（17），从而 以在至少整个存储部分形成区域（100）上连续地延伸。

公开(公告)号：US20100200852A1

公开(公告)日：2010-08-12

申请号：US12709148

申请日：2010-02-19

申请人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

发明人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

IPC分类号： H01L29/68 ,  H01L21/34

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1658 ,  H01L45/1675

摘要： A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

摘要翻译： 设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。 金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及 具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。