公开(公告)号：US20220373738A1

公开(公告)日：2022-11-24

申请号：US17328048

申请日：2021-05-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Steven M. Shank

IPC: G02B6/126 ,  G02B6/27 ,  G02B6/125 ,  G02B6/122

Abstract: Structures for a polarization rotator and methods of fabricating a structure for a polarization rotator. The structure includes a substrate, a first waveguide core over the substrate, and a second waveguide core over the substrate. The second waveguide core is positioned proximate to the section of the first waveguide core. The second waveguide core is comprised of a material having a refractive index that is reversibly variable in response to a stimulus.

公开(公告)号：US20220367360A1

公开(公告)日：2022-11-17

申请号：US17879574

申请日：2022-08-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08

Abstract: A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.

公开(公告)号：US20220352401A1

公开(公告)日：2022-11-03

申请号：US17863922

申请日：2022-07-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Rajendran KRISHNASAMY ,  Steven M. SHANK ,  John J. ELLIS-MONAGHAN ,  Ramsey HAZBUN

IPC: H01L31/0352 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/103 ,  H01L31/028

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with an integrated, light focusing elements and methods of manufacture. The structure includes: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface.

公开(公告)号：US20220350079A1

公开(公告)日：2022-11-03

申请号：US17306334

申请日：2021-05-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Abdelsalam Aboketaf ,  Yusheng Bian

IPC: G02B6/122 ,  G02B6/125 ,  G02B6/13

Abstract: Structures for a photodetector or terminator and methods of fabricating a structure for a photodetector or terminator. The structure includes a waveguide core having a longitudinal axis, a pad connected to the waveguide core, and a light-absorbing layer on the pad adjacent to the waveguide core. The light-absorbing layer includes an annular portion, a first taper, and a second taper laterally spaced from the first taper. The first taper and the second taper are positioned adjacent to the waveguide core.

公开(公告)号：US11487059B2

公开(公告)日：2022-11-01

申请号：US17179532

申请日：2021-02-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Asli Sahin ,  Karen A. Nummy ,  Thomas Houghton ,  Kevin K. Dezfulian ,  Kenneth J. Giewont ,  Yusheng Bian

IPC: G02B6/122 ,  G02B6/13

Abstract: A photonics integrated circuit includes a semiconductor substrate; a buried insulator layer positioned over the semiconductor substrate; and a back-end-of-line (BEOL) insulator stack over a first portion of the buried insulator layer. In addition, the PIC includes a silicon nitride (SiN) waveguide edge coupler positioned in a first region over the buried insulator layer and at least partially under the BEOL insulator stack. An oxide layer extends over a side of the BEOL insulator stack. The SiN waveguide edge coupler provides better power handling and fabrication tolerance than silicon waveguide edge couplers, despite the location under various BEOL layers. The PIC can also include silicon waveguide edger coupler(s).

公开(公告)号：US20220344212A1

公开(公告)日：2022-10-27

申请号：US17861450

申请日：2022-07-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Hui ZANG ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088 ,  H01L29/78

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.

公开(公告)号：US20220326434A1

公开(公告)日：2022-10-13

申请号：US17227843

申请日：2021-04-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/122 ,  G02B6/13

Abstract: Structures for an optical component of a photonics chip and methods of forming a structure for an optical component of a photonics chip. The structure includes a slotted waveguide component having a first and second waveguide cores over a dielectric layer. The first waveguide core separated from the second waveguide core by a slot. The structure further includes a third waveguide core over the dielectric layer. The third waveguide core is positioned in a different level relative to the dielectric layer than the slotted waveguide component, and the third waveguide core and the first slot have an overlapping arrangement

公开(公告)号：US11469178B2

公开(公告)日：2022-10-11

申请号：US17126921

申请日：2020-12-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  John J. Pekarik ,  Vibhor Jain

IPC: H01L23/525 ,  H01L27/12 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a metal-free fuse structure and methods of manufacture. The structure includes: a first metal-free fuse structure comprising a top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material including end portions with a first electrical resistance and a fuse portion of a second, higher electrical resistance electrically connected to the end portions; and a second metal-free fuse structure comprising the top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material of the second metal-free fuse structure including at least a fuse portion of a lower electrical resistance than the second, higher electrical resistance.

公开(公告)号：US11468146B2

公开(公告)日：2022-10-11

申请号：US16705434

申请日：2019-12-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob

IPC: G11C11/408 ,  G06F17/16 ,  H01L27/108 ,  H01L27/146 ,  G11C11/4094 ,  G11C17/06 ,  G11C13/00 ,  G06N3/063

Abstract: Disclosed are embodiments of an integrated circuit structure (e.g., a processing chip), which includes an array of integrated pixel and memory cells configured for deep in-sensor, in-memory computing (e.g., of neural networks). Each cell incorporates a memory structure (e.g., DRAM structure or a ROM structure) with a storage node, which stores a first data value (e.g., a binary weight value), and a sensor connected to a sense node, which outputs a second data value (e.g., an analog input value). Each cell is selectively operable in a functional computing mode during which the voltage level on a bit line is adjusted as a function of both the first data value and the second data value. Each cell is further selectively operable in a storage node read mode. Furthermore, depending upon the type of memory structure (e.g., a DRAM structure), each cell is selectively operable in a storage node write mode.

公开(公告)号：US11456382B2

公开(公告)日：2022-09-27

申请号：US16664056

申请日：2019-10-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.