公开(公告)号：US20210240898A1

公开(公告)日：2021-08-05

申请号：US17053550

申请日：2019-08-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nan ZHANG ,  Jing ZHOU ,  Hao WANG ,  Zhan GAO ,  Maoqian ZHU ,  Cheng ZHOU ,  Zhijin LI ,  Lin WU ,  Shuming GUO ,  Yong HUANG

IPC: G06F30/367 ,  G06F30/392

Abstract: The present application relates to a resistance simulation method for a power device, comprising: establishing an equivalent resistance model of a power device, wherein the connection relationship of N fingers is equivalent to N resistors Rb connected in parallel, input ends of adjacent resistors Rb are connected by means of a resistor Ra, output ends of adjacent resistors Rb are connected by means of a resistor Rc, R a = 1 N ⁢ R 0 , R c = 1 N ⁢ R 1 , and Rb=RDEV*N+RS+RD, wherein R0 and R1 are respectively resistances of a source metal strip and a drain metal strip, Rs is a metal resistor of a first intermediate layer connecting one source region to the source metal strip, RD is a metal resistor of a second intermediate layer connecting one drain region to the drain metal strip, and RDEV is the channel resistance of the power device; and calculating the resistance of the equivalent resistance model as the resistance of the power device.

公开(公告)号：US20210167191A1

公开(公告)日：2021-06-03

申请号：US17265587

申请日：2019-10-14

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan Gu ,  Shikang Cheng ,  Sen Zhang

IPC: H01L29/66 ,  H01L29/78

Abstract: A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.

公开(公告)号：US20210036150A1

公开(公告)日：2021-02-04

申请号：US16645139

申请日：2018-09-01

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nailong HE ,  Sen ZHANG ,  Xuchao LI

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06

Abstract: A lateral double-diffused metal oxide semiconductor component and a manufacturing method therefor. The lateral double-diffused metal oxide semiconductor component comprises: a semiconductor substrate, the semiconductor substrate being provided thereon with a drift area; the drift area being provided therein with a trap area and a drain area, the trap area being provided therein with an active area and a channel; the drift area being provided therein with a deep trench isolation structure arranged between the trap area and the drain area, and the deep trench isolation structure being provided at the bottom thereof with alternately arranged first p-type injection areas and first n-type injection areas.

公开(公告)号：US20210005598A1

公开(公告)日：2021-01-07

申请号：US16766635

申请日：2018-11-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Guangyang WANG

IPC: H01L27/02

Abstract: Provided by the present disclosure is a bidirectional electrostatic discharge protection device which includes a first doped region, a second doped region, a third doped region, a first diode and a second diode. The first doped region has a first conductivity type, and the second doped region and the third doped region both have a second conductivity type. The first doped region has a ring structure outside the second doped region and the third doped region. A cathode of the first diode is coupled to the first doped region, and an anode of the first diode is coupled to a first port together with the second doped region. A cathode of the second diode is coupled to the first doped region, and an anode of the second diode is coupled to a second port together with the third doped region.

公开(公告)号：US20200336076A1

公开(公告)日：2020-10-22

申请号：US16959116

申请日：2018-12-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Qinsong QIAN ,  Shengyou XU ,  Feng LIN ,  Hao WANG ,  Wei SU ,  Qi LIU ,  Longxing SHI

IPC: H02M3/335

Abstract: A control system for synchronous rectifying transistor of LLC converter, the system comprising a voltage sampling circuit, a high-pass filtering circuit, a PI compensation and effective value detection circuit, and a control system taking a microcontroller (MCU) as a core. When the LLC converter is operating at a high frequency, a drain-source voltage VDS(SR) of the synchronous rectifying transistor delivers, via the sampling circuit, a change signal of the drain-source voltage during turn-off into the high-pass filtering circuit and the PI compensation and effective value detection circuit to obtain an effective value amplification signal of a drain-source voltage oscillation signal caused by parasitic parameters, and the current value is compared with a previously collected value via a control circuit taking a microcontroller (MCU) as a core, so as to change a turning-on time of the synchronous rectifying transistor in the next period.

公开(公告)号：US10811520B2

公开(公告)日：2020-10-20

申请号：US16462432

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device, includes: forming a well region (201) in a semiconductor substrate (200) and forming a channel region (202) in the well region (201), and forming a gate oxide layer (210) and a polysilicon layer (220) on the well region (201); etching a portion of the gate oxide layer (210) and the polysilicon layer (220), and exposing a first opening (221) used for forming a source region and a second opening (223) used for forming a drain region; forming a first dielectric layer (230) and a second dielectric layer (240) on the polysilicon layer (220) and in the first opening (221) and the second opening (223) successively, and forming a source region side wall at a side surface of the first opening (221) and forming a drain region side wall at a side surface of the second opening (223); forming a dielectric oxide layer (250) on the polysilicon layer (220), etching the dielectric oxide layer and retaining the dielectric oxide layer (250) located on the drain region side wall; removing the second dielectric layer (240) in the source region side wall and retaining the first dielectric layer (230) therein.

公开(公告)号：US10801839B2

公开(公告)日：2020-10-13

申请号：US15747882

申请日：2016-05-11

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huagang Wu ,  Xueyan Wang

IPC: G01C19/5776 ,  G01P15/08 ,  G01P15/12 ,  G01P15/18

Abstract: An accelerator comprises: an accelerometer (100), configured to detect an acceleration of a motion of a carrier and output a corresponding electrical signal; a sampling and low-pass filter (200), coupled to the accelerometer (100), and configured to sample the electrical signal regularly and filter a noise from the electrical signal; an amplifier (300), configured to amplify the electrical signal after filtering the noise; an analog-to-digital converter (400), configured to convert the amplified electrical signal into a digital signal; a function control module (500), configured to process the digital signal and output a control signal to control the analog-to-digital converter (400), the amplifier (300), and the sampling and low-pass filter (200); and an oscillator module (600), configured to output, according to the control signal, a sampling signal to the sampling and low-pass filter (200), so as to control the sampling and low-pass filter (200) to sample the electrical signal regularly.

公开(公告)号：US20200220010A1

公开(公告)日：2020-07-09

申请号：US16644856

申请日：2018-08-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Guipeng SUN ,  Hongfeng JIN

IPC: H01L29/78 ,  H01L29/66

Abstract: Provided in the present invention are an LDMOS component, a manufacturing method therefor, and an electronic device, comprising: a semiconductor substrate (100); a drift area (101) provided in the semiconductor substrate; a gate electrode structure (103) provided on a part of the surface of the semiconductor substrate and covers a part of the surface of the drift area; a source electrode (1052) and a drain electrode (1051) respectively provided in the semiconductor substrate on either side of the gate electrode structure, where the drain electrode is provided in the drift area and is separated from the gate electrode structure; a metal silicide barrier layer (106) covering the surface of at least a part of the semiconductor substrate between the gate electrode structure and the drain electrode; and a first contact hole (1081) provided on the surface of at least a part of the metal silicide barrier layer.

公开(公告)号：US20200013864A1

公开(公告)日：2020-01-09

申请号：US16483396

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: A gate structure of a semiconductor device, includes: a trench gate and a planar gate including a plurality of polysilicon structures (406) separated from each other; the gate structure of the semiconductor device further includes a well region (503) being adjacent to the trench gate and being disposed under the planar gate; a first conduction type doped region (504) being disposed in the well region (503) and including a plurality of regions separated from each other, wherein each region is disposed under adjacent polysilicon structures (406), and respective regions are electrically connected to the planar gate; and a source (504a) being disposed in the well region (503); wherein the trench gate includes: a silicon oxide filler (202) including a side wall silicon oxide and a bottom silicon oxide; a control gate (402) being located over the trench gate, wherein a side wall of the control gate is enclosed by the side wall silicon oxide, and the control gate (402) is electrically-connected to the planar gate; a shield gate (404) having a single segment structure or a longitudinally arranged multiple segments structure; and an insulation silicon oxide (204) being filled between adjacent control gate and shield gate in vertical direction.

公开(公告)号：US20190221560A1

公开(公告)日：2019-07-18

申请号：US16329348

申请日：2017-08-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Shikang CHENG ,  Sen ZHANG

IPC: H01L27/07 ,  H01L21/8234

CPC classification number: H01L27/0705 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823493 ,  H01L27/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/808

Abstract: A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (214); a JFET source (210), which is of a first conduction type and formed within the well region; a metal electrode (212) of the JFET sources formed on the JFET sources (210), which is in contact with the JFET sources (210); a lateral channel region (208), which is of the first conduction type and formed between two adjacent JFET sources (210), while two ends thereof are in contact with the two adjacent JFET sources (210); and a JFET metal gate (213) formed on the well region.