公开(公告)号：US20140124840A1

公开(公告)日：2014-05-08

申请号：US13670674

申请日：2012-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

公开(公告)号：US08703557B1

公开(公告)日：2014-04-22

申请号：US13863044

申请日：2013-04-15

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/84 ,  H01L21/00

CPC classification number: H01L29/6681 ,  H01L21/823821

Abstract: One method disclosed herein includes forming a plurality of fin-formation trenches in a substrate that defines a plurality of fins, wherein at least one of the fins is a dummy fin, forming an insulating material that fills at least a portion of the trenches, forming a recess in a masking layer formed above the insulating material, forming a sidewall spacer on sidewalls of the recess so as to define a spacer opening, performing at least one first etching process on the masking layer through the spacer opening to define an opening in the masking layer that exposes a portion of the insulating material and the dummy fin, and performing at least one second etching process to remove at least a portion of the dummy fin and thereby define an opening in the insulating material.

Abstract translation: 本文公开的一种方法包括在限定多个翅片的基底中形成多个翅片形成沟槽，其中至少一个翅片是虚拟翅片，形成填充沟槽的至少一部分的绝缘材料，形成 在绝缘材料上形成的掩模层中的凹槽，在凹槽的侧壁上形成侧壁间隔物，以限定间隔开口，通过间隔开口在掩模层上执行至少一个第一蚀刻工艺，以在 暴露绝缘材料和虚拟鳍片的一部分的掩模层，并且执行至少一个第二蚀刻工艺以去除所述虚拟鳍片的至少一部分，从而限定所述绝缘材料中的开口。

公开(公告)号：US20140042502A1

公开(公告)日：2014-02-13

申请号：US13957587

申请日：2013-08-02

Applicant: Globalfoundries Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

Abstract: One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

Abstract translation: 本文公开的一种说明性方法包括去除牺牲侧壁间隔物的一部分，从而暴露牺牲栅电极的侧壁的至少一部分，并在牺牲栅电极的暴露的侧壁上形成衬垫层。 在该示例中，该方法还包括在衬垫层之上形成牺牲间隙填充材料，暴露和去除牺牲栅极电极，从而限定由衬里层横向限定的栅极腔，形成替代栅极结构，去除牺牲层 间隙填充材料并形成邻近衬层的低k侧壁间隔物。 还公开了一种器件，其包括栅极覆盖层，位于栅极绝缘层的两个直立部分中的每一个上的氮化硅或氮氧化硅层，以及位于氮化硅或氮氧化硅层上的低k侧壁间隔物。

公开(公告)号：US10290636B2

公开(公告)日：2019-05-14

申请号：US14461769

申请日：2014-08-18

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Chun-chen Yeh ,  Ruilong Xie ,  Xiuyu Cai

IPC: H01L27/092 ,  H01L29/167 ,  H01L29/161 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/06

Abstract: A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material. In addition, at least one first fin may be formed from the first semiconductor region, and at least one second fin may be formed from the second semiconductor region, the punch-through stopper layer, the semiconductor buffer layer, and the third semiconductor region.

公开(公告)号：US10256304B2

公开(公告)日：2019-04-09

申请号：US15890880

申请日：2018-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/41 ,  H01L29/66 ,  H01L21/306 ,  H01L29/20 ,  H01L29/417

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

公开(公告)号：US10134840B2

公开(公告)日：2018-11-20

申请号：US14739543

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Chun-Chen Yeh ,  Xiuyu Cai ,  Qing Liu ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10

Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

公开(公告)号：US20180219096A1

公开(公告)日：2018-08-02

申请号：US15936149

申请日：2018-03-26

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/02 ,  H01L21/321 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/0217 ,  H01L21/28141 ,  H01L21/3212 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/785 ,  H01L29/78654

Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.

公开(公告)号：US20180190787A1

公开(公告)日：2018-07-05

申请号：US15904982

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Ying Hao Hsieh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165

CPC classification number: H01L29/6656 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.

公开(公告)号：US10014299B2

公开(公告)日：2018-07-03

申请号：US15170134

申请日：2016-06-01

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Xiuyu Cai ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L27/00 ,  H01L27/092 ,  H01L29/16 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.

公开(公告)号：US10008415B2

公开(公告)日：2018-06-26

申请号：US15419346

申请日：2017-01-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

IPC: H01L21/84 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.