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公开(公告)号：US10957544B2
公开(公告)日：2021-03-23
申请号：US15484173
申请日：2017-04-11
发明人： Andrew M. Greene , Ryan O. Jung , Ruilong Xie
IPC分类号： H01L21/283 , H01L29/66 , H01L21/28 , H01L21/311 , H01L27/02 , H01L21/033 , H01L21/3105
摘要： A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.
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公开(公告)号：US10797154B2
公开(公告)日：2020-10-06
申请号：US15190778
申请日：2016-06-23
IPC分类号： H01L21/768 , H01L29/66 , H01L21/283 , H01L27/088 , H01L29/417 , H01L23/485 , H01L29/78 , H01L23/532 , H01L23/535 , H01L21/306 , H01L21/8234 , H01L29/08
摘要： A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.
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公开(公告)号：US10734499B2
公开(公告)日：2020-08-04
申请号：US15986031
申请日：2018-05-22
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie , Tenko Yamashita
IPC分类号： H01L29/66 , H01L29/06 , H01L29/78 , H01L29/10 , H01L21/3065 , H01L21/308 , H01L21/20 , H01L21/3105 , H01L21/8234 , H01L27/088
摘要： Methods for forming a semiconductor device include forming a first spacer on a plurality of fins. A second spacer is formed on the first spacer, the second spacer being formed from a different material from the first spacer. Gaps between the fins are filled with a support material. The first spacer and second spacer are polished to expose a top surface of the plurality of fins. All of the support material is etched away after polishing the first spacer and second spacer. The plurality of fins is etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.
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公开(公告)号：US10431682B2
公开(公告)日：2019-10-01
申请号：US15693952
申请日：2017-09-01
发明人： Qing Liu , Ruilong Xie , Chun-chen Yeh
IPC分类号： H01L29/78 , H01L29/66 , H01L21/306 , H01L21/02 , H01L21/324 , H01L29/417
摘要： A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
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公开(公告)号：US10355086B2
公开(公告)日：2019-07-16
申请号：US15181843
申请日：2016-06-14
发明人： Xiuyu Cai , Qing Liu , Kejia Wang , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/84 , H01L29/10 , H01L29/66 , H01L21/306 , H01L29/20 , H01L29/417 , H01L29/78
摘要： A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
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公开(公告)号：US20190206868A1
公开(公告)日：2019-07-04
申请号：US16294117
申请日：2019-03-06
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L27/092 , H01L29/06 , H01L29/16 , H01L21/8238 , H01L21/033 , H01L21/308 , H01L29/78 , H01L29/165 , H01L29/10 , H01L27/12 , H01L21/84
CPC分类号： H01L27/0924 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0922 , H01L27/1211 , H01L29/0684 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/7849
摘要： A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
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7.发明授权公开(公告)号：US10340189B2
公开(公告)日：2019-07-02
申请号：US15689565
申请日：2017-08-29
IPC分类号： H01L29/51 , H01L21/8234 , H01L29/08 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/417 , H01L29/78 , H01L29/10 , H01L21/84 , H01L27/12
摘要： A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.
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公开(公告)号：US10217869B2
公开(公告)日：2019-02-26
申请号：US15936149
申请日：2018-03-26
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie
IPC分类号： H01L29/66 , H01L29/51 , H01L29/78 , H01L21/02 , H01L21/321 , H01L29/423 , H01L21/28 , H01L29/786
摘要： A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.
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公开(公告)号：US10186599B1
公开(公告)日：2019-01-22
申请号：US15655547
申请日：2017-07-20
申请人： International Business Machines Corporation , GLOBALFOUNDRIES Inc. , SAMSUNG ELECTRONICS CO., LTD.
发明人： Su Chen Fan , Andrew M. Greene , Sean Lian , Balasubramanian Pranatharthiharan , Mark V. Raymond , Ruilong Xie
IPC分类号： H01L21/82 , H01L29/66 , H01L21/033 , H01L21/768 , H01L21/285 , H01L29/49 , H01L29/51
摘要： Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.
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公开(公告)号：US10096674B2
公开(公告)日：2018-10-09
申请号：US15717336
申请日：2017-09-27
发明人： Kangguo Cheng , Xin Miao , Ruilong Xie , Tenko Yamashita
IPC分类号： H01L29/06 , H01L27/12 , H01L29/423 , H01L29/786 , H01L29/775 , H01L29/66 , H01L21/02 , H01L21/265 , H01L21/84 , H01L21/8238 , H01L27/092
摘要： A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.
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