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    FIELD EFFECT TRANSISTOR CONSTRUCTIONS AND MEMORY ARRAYS
    211.
    发明申请
    FIELD EFFECT TRANSISTOR CONSTRUCTIONS AND MEMORY ARRAYS 有权
    场效应晶体管结构和存储器阵列

    公开(公告)号：US20150200202A1

    公开(公告)日：2015-07-16

    申请号：US14152664

    申请日：2014-01-10

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

    IPC: H01L27/115 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/0603 ,  H01L29/24 ,  H01L29/66666

    Abstract: A field effect transistor construction comprises two source/drain regions and a channel region there-between. The channel region comprises a transition metal dichalcogenide material having a thickness of 1 monolayer to 7 monolayers and having a physical length between the source/drain regions. A mid-gate is operatively proximate a mid-portion of the channel region relative to the physical length. A pair of gates is operatively proximate different respective portions of the channel region from the portion of the channel region that the mid-gate is proximate. The pair of gates are spaced and electrically isolated from the mid-gate on opposite sides of the mid-gate. Gate dielectric is between a) the channel region, and b) the mid-gate and the pair of gates. Additional embodiments are disclosed.

    Abstract translation: 场效应晶体管结构包括两个源极/漏极区域和其间的沟道区域。 通道区域包含厚度为1单层至7层的过渡金属二硫属元素材料，并且在源极/漏极区域之间具有物理长度。 中间栅极相对于物理长度可操作地邻近沟道区的中部。 一对门可操作地接近沟道区域与中栅极接近的沟道区域的部分的不同相应部分。 一对门与中门对面的中间门隔开并与之隔离。 栅极电介质位于a）沟道区域之间，b）中间栅极与栅极对之间。 公开了另外的实施例。

    Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith
    213.
    发明申请
    Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith 有权
    形成垂直晶体管的方法和至少一个导电线电耦合的方法

    公开(公告)号：US20130237023A1

    公开(公告)日：2013-09-12

    申请号：US13869112

    申请日：2013-04-24

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

    IPC: H01L21/8234

    CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

    Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

    Abstract translation: 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

    DISCHARGING AN ACCESS DEVICE IN A MEMORY DEVICE
    216.
    发明申请
    DISCHARGING AN ACCESS DEVICE IN A MEMORY DEVICE 有权

    公开(公告)号：US20250078903A1

    公开(公告)日：2025-03-06

    申请号：US18790372

    申请日：2024-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Huy T. Vo ,  Eric Carman ,  Kamal M. Karda

    IPC: G11C11/4074 ,  G11C11/4091 ,  H10B12/00

    Abstract: Systems, methods, and apparatus are provided for discharging an access device in a memory device. An example structure includes a memory device having a local sense line and a bleeder device coupled to the local sense line and a bleeder supply. The memory device can also include a sense line multiplexor coupled to the local sense line and a global sense line, and a sense amplifier coupled to the global sense line. The sense amplifier can be configured to sense and latch a voltage of the global sense line in response to the memory device receiving a command. The memory device can further include a plurality of access devices coupled to the local sense line, a plurality of capacitors coupled to the plurality of access devices, and a plate voltage supply, separate from the bleeder supply, coupled to the plurality of capacitors.

    Memory device having memory cell strings and separate read and write control gates
    217.
    发明授权
    Memory device having memory cell strings and separate read and write control gates 有权

    公开(公告)号：US12200928B2

    公开(公告)日：2025-01-14

    申请号：US17387669

    申请日：2021-07-28

    Applicant: Micron Technology, Inc.

    Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin ,  Yingda Dong

    IPC: H10B43/27 ,  H01L21/28 ,  H01L29/423 ,  H10B41/27

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES
    219.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES 有权

    公开(公告)号：US20240420750A1

    公开(公告)日：2024-12-19

    申请号：US18818295

    申请日：2024-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E. Fackenthal ,  Duane R. Mills

    IPC: G11C11/404

    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

    TWO TRANSISTOR CELLS FOR VERTICAL THREE-DIMENSIONAL MEMORY HAVING VERICAL DIGIT LINES
    220.
    发明公开
    TWO TRANSISTOR CELLS FOR VERTICAL THREE-DIMENSIONAL MEMORY HAVING VERICAL DIGIT LINES 审中-公开

    公开(公告)号：US20240357794A1

    公开(公告)日：2024-10-24

    申请号：US18645043

    申请日：2024-04-24

    Applicant: Micron Technology, Inc.

    Inventor： Litao Yang ,  Haitao Liu ,  Kamal M. Karda ,  Si-Woo Lee

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: Systems, methods and apparatus are provided for two transistor cells for vertical three-dimensional memory. The memory has pairs of serially connected transistors, each pair of serially connected transistors having an independent first source/drain region and a shared second source/drain region separated by channel regions; horizontally oriented access lines separated from the channel regions by a gate dielectric material; and vertically oriented digit lines electrically coupled to the first source/drain regions of the serially connected transistors.

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