公开(公告)号：US20150108577A1

公开(公告)日：2015-04-23

申请号：US14056144

申请日：2013-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Hoon Kim ,  Xunyuan Zhang

IPC: H01L21/28 ,  H01L29/49 ,  H01L27/092 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517

Abstract: Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device.

Abstract translation: 公开了形成半导体器件的替代金属栅极（RMG）的方法。 具体地提供了在衬底上形成的p沟道场效应晶体管（p-FET）和n沟道场效应晶体管（n-FET），其中形成有凹部的p-FET和n-FET， 高k层和在每个凹槽内形成的阻挡层，选择性地生长在n-FET的凹槽内的功函数金属（WFM），其中高k层，势垒层和WFM各自凹入到期望的 在凹部内的高度，以及形成在每个凹部内的金属材料（例如，钨）。 通过在该方法中较早提供WFM倒角，减少了掩模材料填充到每个浇口凹槽中的风险。 此外，选择性WFM生长改善了金属材料的填充，这降低了器件中的栅极电阻。

公开(公告)号：US20150035086A1

公开(公告)日：2015-02-05

申请号：US13957991

申请日：2013-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Larry Zhao

IPC: H01L29/66 ,  H01L29/51

CPC classification number: H01L23/53295 ,  H01L23/535 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed herein includes forming an etch stop layer above recessed sidewall spacers and a recessed replacement gate structure and, with the etch stop layer in position, forming a self-aligned contact that is conductively coupled to the source/drain region after forming the self-aligned contact. A device disclosed herein includes an etch stop layer that is positioned above a recessed replacement gate structure and recessed sidewall spacers, wherein the etch stop layer defines an etch stop recess that contains a layer of insulating material positioned therein. The device further includes a self-aligned contact.

Abstract translation: 本文公开的一种方法包括在凹陷的侧壁间隔物和凹入的替换栅极结构上方形成蚀刻停止层，并且将蚀刻停止层置于适当位置，形成在形成自身之后与源/漏区导电耦合的自对准接触 联系人。 本文公开的装置包括位于凹入的替代栅极结构和凹陷的侧壁间隔物之上的蚀刻停止层，其中蚀刻停止层限定了包含定位在其中的绝缘材料层的蚀刻停止凹部。 该装置还包括自对准接触件。

公开(公告)号：US08946793B2

公开(公告)日：2015-02-03

申请号：US13759209

申请日：2013-02-05

Applicant: Globalfoundries, Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/40 ,  H01L29/49

CPC classification number: H01L21/28114 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method of fabricating an integrated circuit includes forming an interlayer dielectric (ILD) layer over a dummy gate stack. The dummy gate stack includes a dummy gate structure, a hardmask layer, and sidewall spacers formed over a semiconductor substrate. The method further includes removing at least an upper portion of the dummy gate stack to form a first opening within the ILD layer, extending the first opening to form a first extended opening by completely removing the dummy gate structure of the dummy gate stack, and depositing at least one workfunction material layer within the first opening and within the first extended opening. Still further, the method includes removing portions of the workfunction material within the first opening and depositing a low-resistance material over remaining portions of the workfunction material thereby forming a replacement metal gate structure that includes the remaining portion of the workfunction material and the low-resistance material.

Abstract translation: 制造集成电路的方法包括在虚拟栅极堆叠上形成层间电介质（ILD）层。 虚拟栅极堆叠包括伪栅极结构，硬掩模层和形成在半导体衬底上的侧壁间隔物。 该方法还包括去除伪栅极堆叠的至少上部以在ILD层内形成第一开口，通过完全去除虚拟栅极堆叠的伪栅极结构，延伸第一开口以形成第一扩展开口，并且沉积 在所述第一开口内和所述第一延伸开口内的至少一个功函数材料层。 此外，该方法包括去除第一开口内的功函件材料的一部分，并在工作功能材料的剩余部分上沉积低电阻材料，从而形成包括功函件材料和低功能材料的剩余部分的替换金属栅结构， 电阻材料。

公开(公告)号：US08946075B2

公开(公告)日：2015-02-03

申请号：US13785468

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  John A. Iacoponi

IPC: H01L21/4763 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/76831 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively forming an oxidizable material in the gate recess, converting the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to a source/drain region. A device includes an oxide material that is positioned at least partially in a recess formed in a gate structure, wherein the oxide material contacts a conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.

Abstract translation: 一种方法包括执行第一蚀刻工艺以在暴露晶体管的栅极结构的一部分的绝缘材料层中形成接触开口，对栅极结构的暴露部分执行第二蚀刻工艺，由此限定栅极凹部 在所述栅极凹槽中选择性地形成可氧化材料，将所述可氧化材料转化为氧化物材料，以及在与所述源极/漏极区域导电耦合的所述接触开口中形成导电接触。 一种器件包括至少部分地位于形成在栅极结构中的凹部中的氧化物材料，其中氧化物材料接触导电接触并接触栅极结构的外表面的一部分但并非全部。

公开(公告)号：US08883631B1

公开(公告)日：2014-11-11

申请号：US13905271

申请日：2013-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Xiuyu Cai

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/76804

Abstract: One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material, forming a layer of sacrificial material so as to overfill the cavity, performing at least one planarization process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity.

Abstract translation: 本文公开的一种说明性方法包括在导电结构之上形成至少一层绝缘材料，形成由绝缘材料层上方的金属构成的图案化硬掩模，执行至少一个蚀刻工艺以在绝缘材料层中限定空腔 形成牺牲材料层以便过度填充空腔，执行至少一个平坦化处理以去除牺牲材料层和图案化的硬掩模的一部分，同时将牺牲材料层的剩余部分留在空腔内， 以及去除位于腔内的牺牲材料层的剩余部分。

公开(公告)号：US20140327089A1

公开(公告)日：2014-11-06

申请号：US14333683

申请日：2014-07-17

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0207 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin.

Abstract translation: 一种方法包括通过图案化的掩模层执行蚀刻工艺，以在限定第一和第二鳍片的衬底中形成沟槽，将邻近第一鳍片的衬垫材料形成第一厚度，将与第二鳍片相邻的衬垫材料形成为不同于第二厚度的第二厚度 所述第一厚度在所述沟槽中形成绝缘材料，所述沟槽邻近所述衬垫材料并且在所述掩模层上方，执行处理操作以去除所述绝缘材料层的部分并暴露所述衬垫材料的部分，执行另一蚀刻工艺以去除部分 所述衬垫材料和所述掩模层将所述第一翅片暴露于第一高度，并且所述第二鳍片具有不同于所述第一高度的第二高度，执行另一蚀刻工艺以限定绝缘材料的厚度减薄层，以及形成栅极结构 围绕第一和第二鳍的一部分。

公开(公告)号：US08871582B2

公开(公告)日：2014-10-28

申请号：US13839626

申请日：2013-03-15

Applicant: GlobalFoundries Inc. ,  International Business Machines Corporation

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/4232 ,  H01L21/28247 ,  H01L29/66545 ,  H01L29/78

Abstract: One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material.

Abstract translation: 一种方法包括形成凹入的栅极/间隔结构，其部分地限定间隔物/栅极盖凹部，在间隔物/栅极盖凹部中形成栅极盖层，在栅极盖层的上表面上形成栅极盖保护层，以及 去除栅极帽保护层的部分，留下栅极盖保护层的一部分位于栅极盖层的上表面上。 本文公开的装置包括定位在绝缘材料层中的栅极/间隔结构，位于栅极/间隔物结构上的栅极盖层，其中栅极盖层的侧壁接触绝缘材料层，栅极盖保护层 定位在栅极盖层的上表面上，其中栅极盖保护层的侧壁也接触绝缘材料层。

公开(公告)号：US20140264487A1

公开(公告)日：2014-09-18

申请号：US13839802

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract translation: 本文公开的一种方法包括形成封装并保护栅极盖层的第一和第二栅极盖保护层。 本文公开的新型晶体管器件包括位于半导体衬底上方的栅极结构，邻近栅极结构定位的间隔结构，位于衬底上方并围绕间隔结构的绝缘材料层，位于栅极结构之上的栅极盖层， 所述间隔结构以及封装所述栅极盖层的栅极帽保护材料，其中所述栅极盖保护材料的部分位于所述栅极盖层和所述栅极结构之间，所述间隔物结构和所述绝缘材料层。

公开(公告)号：US20140252425A1

公开(公告)日：2014-09-11

申请号：US13785468

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  John A. Iacoponi

IPC: H01L21/768 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/76831 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively forming an oxidizable material in the gate recess, converting the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to a source/drain region. A device includes an oxide material that is positioned at least partially in a recess formed in a gate structure, wherein the oxide material contacts a conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.

Abstract translation: 一种方法包括执行第一蚀刻工艺以在暴露晶体管的栅极结构的一部分的绝缘材料层中形成接触开口，对栅极结构的暴露部分执行第二蚀刻工艺，由此限定栅极凹部 在所述栅极凹槽中选择性地形成可氧化材料，将所述可氧化材料转化为氧化物材料，以及在与所述源极/漏极区域导电耦合的所述接触开口中形成导电接触。 一种器件包括至少部分地位于形成在栅极结构中的凹部中的氧化物材料，其中氧化物材料接触导电接触并接触栅极结构的外表面的一部分但并非全部。

公开(公告)号：US20140217517A1

公开(公告)日：2014-08-07

申请号：US13759156

申请日：2013-02-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L29/7853 ,  H01L21/28 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，集成电路包括半导体衬底。 第一翅片和第二翅片彼此相邻，从半导体衬底延伸。 第一翅片具有第一上部，第二翅片具有第二上部。 第一外延部分覆盖第一上部，第二外延部分覆盖第二上部。 第一硅化物层覆盖第一外延部分，第二硅化物层覆盖第二外延部分。 第一和第二硅化物层彼此间隔开以限定横向间隙。 电介质隔离物由电介质材料形成并横跨横向间隙。 接触形成材料覆盖介质间隔物和第一和第二硅化物层的在电介质间隔物的横向上方的部分。