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    Clock recovery from data streams containing embedded reference clock values
    211.
    发明申请
    Clock recovery from data streams containing embedded reference clock values 有权
    从包含嵌入式参考时钟值的数据流中恢复时钟

    公开(公告)号：US20030086518A1

    公开(公告)日：2003-05-08

    申请号：US10285329

    申请日：2002-10-30

    Applicant: STMicroelectronics Pvt. Ltd.

    Inventor： Kalyana Chakravarthy

    IPC: H04L007/02 ,  H03D003/24

    CPC classification number: H04N21/4305 ,  H03L7/0992 ,  H03L7/181

    Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source means includes of a controllable digital fractional divider means receiving a control value from digital comparator means and a clock input from a digital clock synthesizer means driven by a fixed oscillator means.

    Abstract translation: 一种用于从包含嵌入式参考时钟值的数据流中恢复时钟的方法和改进装置，所述控制时钟源装置包括从数字比较器装置接收控制值的可控数字分数器装置和由数字比较器装置驱动的数字时钟合成器装置的时钟输入 固定振荡器装置。

    Fractional divider
    212.
    发明申请
    Fractional divider 有权
    分数分频器

    公开(公告)号：US20030076137A1

    公开(公告)日：2003-04-24

    申请号：US10269838

    申请日：2002-10-10

    Applicant: STMicroelectronics Pvt. Ltd.

    Inventor： Kalyana Chakravarthy

    IPC: H03K023/50

    CPC classification number: H03L7/1976 ,  H03K23/68

    Abstract: An improved fractional divider that comprises an integer value storage means containing the integer part of the division value nullKnull connected to the input of a programmable counter means that is configured for a count value of nullKnull or nullKnull1null depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces the count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value.

    Abstract translation: 一种改进的分数分割器，其包括整数值存储装置，其包含连接到可编程计数器装置的输入的除法值“K”的整数部分，该可编程计数器装置被配置用于计数值“K”或“K + 1”，这取决于 计数控制信号的状态，并且产生输出信号以及终端计数信号，该终端计数信号连接到分数累加器装置的使能输入，该分数累加器装置在加法溢出时产生计数控制信号，并且具有连接到其结果输出的第一输入 以及连接到分数值存储装置的输出的第二输入，其包含分频值的小数部分。

    NON-VOLATILE MEMORY DEVICE WITH CLUSTERED MEMORY CELLS
    214.
    发明申请
    NON-VOLATILE MEMORY DEVICE WITH CLUSTERED MEMORY CELLS 有权
    具有聚集的存储器单元的非易失性存储器件

    公开(公告)号：US20140036564A1

    公开(公告)日：2014-02-06

    申请号：US13954908

    申请日：2013-07-30

    Applicant: STMicroelectronics PVT LTD ,  STMicroelectronics S.r.l.

    Inventor： Fabio DE SANTIS ,  Marco PASOTTI ,  Abhishek LAL

    IPC: G11C5/02

    CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C7/18 ,  G11C8/12 ,  G11C16/00 ,  G11C16/08 ,  G11C16/24

    Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.

    Abstract translation: 非易失性存储器件的实施例包括：存储器阵列，其具有布置在至少一个逻辑行中的多个非易失性逻辑存储器单元，所述逻辑行包括共享公共控制线的第一行和第二行; 和多个位线。 每个逻辑存储器单元具有用于存储逻辑值的直接存储单元和用于存储第二逻辑值的互补存储器单元，该第二逻辑值与对应的直接存储器单元中的第一逻辑值互补。 每个逻辑存储单元的直接存储单元和互补存储单元被耦合到相应的单独的位线，并且被放置在相应的逻辑行的第二行中的第一行而另一个中。

    PHASE LOCKED LOOP CIRCUIT WITH REDUCED JITTER
    215.
    发明申请
    PHASE LOCKED LOOP CIRCUIT WITH REDUCED JITTER 有权
    具有减少抖动的相位锁定环路

    公开(公告)号：US20140015577A1

    公开(公告)日：2014-01-16

    申请号：US13547742

    申请日：2012-07-12

    Applicant: Anand KUMAR ,  Pradeep DHADDA

    Inventor： Anand KUMAR ,  Pradeep DHADDA

    IPC: H03L7/08

    CPC classification number: H03L7/093 ,  H03L7/099 ,  H03L7/18 ,  H03L2207/06

    Abstract: A system and method for providing a phase-locked loop that reduces the effects of jitter caused by thermal noise of a resistor in a low-pass filter in the PLL. Thermal noise from various electronic components may cause unwanted jitter is a PLL. The size of various components in the filter are typically set to specific sizes to realize a transfer function suited for loop stability and reduction in phase jitter. In one embodiment, the jitter due to thermal noise in the resistor may be reduced by reducing the size of the gain affecting the signal through this resistor. By adjusting the size of the resistor by a scaling factor as well as other components in the PLL, one may then control a voltage controlled oscillator (VCO) using two or more control signals through the LPF.

    Abstract translation: 一种用于提供锁相环的系统和方法，其减少由PLL中的低通滤波器中的电阻器的热噪声引起的抖动的影响。 来自各种电子部件的热噪声可能会导致不必要的抖动是PLL。 滤波器中的各种组件的尺寸通常设置为特定尺寸，以实现适合于环路稳定性和减少相位抖动的传输功能。 在一个实施例中，可以通过减小影响通过该电阻器的信号的增益的大小来减小由于电阻器中的热噪声引起的抖动。 通过调节电阻器的尺寸以及PLL中的其他部件，可以通过LPF使用两个或多个控制信号来控制压控振荡器（VCO）。

    Differential successive approximation analog to digital converter
    216.
    发明授权
    Differential successive approximation analog to digital converter 有权
    差分逐次逼近模数转换器

    公开(公告)号：US08497795B2

    公开(公告)日：2013-07-30

    申请号：US13166117

    申请日：2011-06-22

    Applicant: Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

    Inventor： Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

    IPC: H03M1/34

    CPC classification number: H03M1/468

    Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.

    Abstract translation: 一种差分逐次逼近模数转换器，包括：比较器; 耦合在对应的多个第一开关和比较器的第一输入之间的第一多个电容器，所述第一电容器中的至少一个被布置为接收差分输入信号的第一分量; 以及耦合在相应的多个第二开关和所述比较器的第二输入之间的第二多个电容器，所述第二电容器中的至少一个布置成接收所述差分输入信号的第二分量，其中所述第一和第二多个 的开关各自适于独立地将相应的电容器耦合到所选择的一个：第一电源电压电平; 第二电源电压; 和第三电源电压电平; 以及控制电路，其适于在采样阶段期间对差分输入电压进行采样，并且控制第一和第二开关以在电压转换阶段开始时将第一和第二多个电容器的每个电容器耦合到第三电源电压电平。

    LOW VOLTAGE WRITE TIME ENHANCED SRAM CELL AND CIRCUIT EXTENSIONS
    217.
    发明申请
    LOW VOLTAGE WRITE TIME ENHANCED SRAM CELL AND CIRCUIT EXTENSIONS 有权
    低电压写时间增强SRAM单元和电路扩展

    公开(公告)号：US20130170289A1

    公开(公告)日：2013-07-04

    申请号：US13339587

    申请日：2011-12-29

    Applicant: Anuj Grover ,  Gangaikondan Subramani Visweswaran

    Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

    IPC: G11C11/412

    CPC classification number: G11C11/412

    Abstract: A memory cell is formed by storage latch coupled between a true bit line node and a complement bit line node. The latch has an internal true node and an internal complement node. The cell additionally includes a first transistor that is source-drain coupled between the internal true node and a word line node. A control terminal of the first transistor is coupled to receive a signal from the complement bit line node and functions to source current into the true node during write mode. The cell further includes a second transistor that is source-drain coupled between the internal complement node and the word line node. A control terminal of the second transistor is coupled to receive a signal from the true bit line node and functions to source current into the complement node during write mode.

    Abstract translation: 存储器单元由耦合在真位线节点和补码位线节点之间的存储锁存器形成。 锁存器具有内部真实节点和内部补码节点。 电池还包括第一晶体管，其是在内部真实节点和字线节点之间耦合的源极 - 漏极。 第一晶体管的控制端子被耦合以从补码位线节点接收信号，并且用于在写入模式期间将电流源流入真实节点。 该单元还包括第二晶体管，其源极 - 漏极耦合在内部补码节点和字线节点之间。 第二晶体管的控制端子被耦合以从真位线节点接收信号，并且用于在写入模式期间将电流源流入补码节点。

    STRESS REDUCED CASCODED CMOS OUTPUT DRIVER CIRCUIT
    218.
    发明申请
    STRESS REDUCED CASCODED CMOS OUTPUT DRIVER CIRCUIT 有权
    应力减小的CMOS输出驱动电路

    公开(公告)号：US20130141140A1

    公开(公告)日：2013-06-06

    申请号：US13310468

    申请日：2011-12-02

    Applicant: Vinod KUMAR

    Inventor： Vinod KUMAR

    IPC: H03B1/00

    CPC classification number: H03K3/02 ,  G11C7/1057 ,  G11C7/1069

    Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

    Abstract translation: 输出驱动器电路包括具有公共电流路径的第一，第二，第三和第四晶体管，其中第一晶体管的栅极接收第一开关信号，第二晶体管的栅极接收第一参考电压，第三晶体管的栅极 晶体管接收第二参考电压，并且第四晶体管的栅极接收第二开关信号，并且其中第一电容器耦合在第一晶体管的栅极和第三晶体管的栅极之间，第二电容器耦合在栅极之间 的第二晶体管和第四晶体管的栅极，并且在耦合第二和第三晶体管的节点处提供输出信号。

    Current steering DAC with switched cascode output current source/sink
    219.
    发明授权
    Current steering DAC with switched cascode output current source/sink 有权
    电流转向DAC，具有开关共源共栅输出电流源/汇

    公开(公告)号：US08441382B2

    公开(公告)日：2013-05-14

    申请号：US13047542

    申请日：2011-03-14

    Applicant: Puneet Mahajan ,  Anand Singh Rawat ,  Anil Kumar

    Inventor： Puneet Mahajan ,  Anand Singh Rawat ,  Anil Kumar

    IPC: H03M1/00

    CPC classification number: H03K17/063 ,  H03K2217/0054 ,  Y10T29/49002

    Abstract: A current-steering digital-to-analog converter may include a plurality of current cells. Each current cell may comprise a dual bias switched cascode output current source/sink, a bias source, complementary bias switching elements coupled between the bias source and the bias inputs of the switched cascode output current source/sink, and complementary switching signals coupled to the control inputs of the complementary bias switching element.

    Abstract translation: 电流转向数模转换器可以包括多个当前单元。 每个当前单元可以包括双偏压开关共源共栅输出电流源/汇，偏置源，耦合在偏置源和开关共源共栅输出电流源/汇的偏置输入之间的互补偏置开关元件，以及耦合到 互补偏置开关元件的控制输入。

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