公开(公告)号：US07375027B2

公开(公告)日：2008-05-20

申请号：US10964317

申请日：2004-10-12

Applicant: Kuei-Chang Tsai ,  Chunyuan Chao ,  Chia-Shun Hsiao

Inventor： Kuei-Chang Tsai ,  Chunyuan Chao ,  Chia-Shun Hsiao

IPC: H01L21/4763

CPC classification number: H01L21/76805 ,  H01L21/76802 ,  H01L21/76831

Abstract: A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an initial etch through an interlayer dielectric is performed to create an initial via which extends toward, but not into the substrate. At least a portion of the protective layer is retained on the substrate. In another step, the final contact via is created. During this step the protective layer is penetrated to open a via to the surface of the semiconductor material.

Abstract translation: 提供了通过半导体材料的表面的接触通孔，该接触通孔具有通过各向异性蚀刻放置在通孔上的电介质层产生的侧壁。 在半导体材料的表面上设置有保护层。 为了保护衬底，进行通过层间电介质的初始蚀刻，以产生向衬底延伸但不延伸到衬底中的初始通孔。 保护层的至少一部分保留在基板上。 在另一步中，创建最终的联系人通道。 在该步骤期间，保护层被穿透以将通孔打开到半导体材料的表面。

公开(公告)号：US07362428B2

公开(公告)日：2008-04-22

申请号：US11121902

申请日：2005-05-05

Applicant: Chung-I Chang ,  Ferris Liu

Inventor： Chung-I Chang ,  Ferris Liu

IPC: G01N21/89

CPC classification number: G01N21/95607 ,  G01N21/9501 ,  G01N2021/4714

Abstract: A highly sensitive defect detection method is disclosed. A medium with a refractive index greater than 1 is formed on a sample. As a result, incident light projected by a defect detecting system attenuates less when reaching the bottom defects. The detection sensitivity of the defect detecting system is enhanced accordingly.

Abstract translation: 公开了一种高灵敏度缺陷检测方法。 在样品上形成折射率大于1的介质。 结果，由缺陷检测系统投射的入射光在达到底部缺陷时衰减较小。 缺陷检测系统的检测灵敏度相应提高。

公开(公告)号：US07358149B2

公开(公告)日：2008-04-15

申请号：US11193150

申请日：2005-07-29

Applicant: Daniel Wang ,  Chunchieh Huang ,  Dong Jun Kim

Inventor： Daniel Wang ,  Chunchieh Huang ,  Dong Jun Kim

IPC: H01L21/425

CPC classification number: H01L27/11526 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11546

Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

Abstract translation: 衬底隔离沟槽（224）形成在半导体衬底（120）中。 通过离子注入将掺杂剂（例如硼）注入到沟槽侧壁中，以抑制沿着侧壁的电流泄漏。 在离子注入期间，晶体管栅极电介质（520）面向离子流，但在随后的热步骤中对栅极电介质的损坏退火。 在一些实施例中，掺杂剂注入是成角度的植入物。 植入物从晶片的相对侧进行，并且因此从每个有效区域的相对侧进行。 每个有源区域包括从一侧注入的区域和从相对侧注入的区域。 两个区域重叠以便于阈值电压调整。

公开(公告)号：US07349289B2

公开(公告)日：2008-03-25

申请号：US11177537

申请日：2005-07-08

Applicant: Jon Allan Faue ,  Steve Eaton ,  Michael Murray

Inventor： Jon Allan Faue ,  Steve Eaton ,  Michael Murray

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C7/1078 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/1096

Abstract: A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

Abstract translation: 用于集成电路存储器的数据总线电路包括用于将存储器与I / O块连接的每个I / O焊盘的4位总线，但每个I / O仅使用两位用于写入。 使用四位每个I / O焊盘进行读取。 在输入数据选通的每个下降沿，最后两位通过总线发送，这样就不需要精确计数输入数据选通脉冲。 数据总线电路兼容DDR1和DDR2工作模式。

公开(公告)号：US20080070371A1

公开(公告)日：2008-03-20

申请号：US11566761

申请日：2006-12-05

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L21/336

CPC classification number: H01L29/1045 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device includes a substrate, a gate electrode, a pair of first impurity regions, a pair of second impurity regions and at least one dummy pattern. The gate electrode is positioned above the substrate. The first impurity regions are positioned in the substrate and near both sides of the gate electrode. The second impurity regions are positioned in the first impurity regions respectively, and the dopant concentration of the first impurity regions is lower than the dopant concentration of the second impurity regions. The dummy pattern is positioned over the first impurity regions and exposes the second impurity regions.

Abstract translation: 半导体器件包括衬底，栅极电极，一对第一杂质区域，一对第二杂质区域和至少一个虚拟图案。 栅电极位于衬底上方。 第一杂质区位于基板中并靠近栅电极的两侧。 第二杂质区域分别位于第一杂质区域中，第一杂质区域的掺杂剂浓度低于第二杂质区域的掺杂剂浓度。 虚设图案位于第一杂质区上方并暴露第二杂质区。

公开(公告)号：US20080048235A1

公开(公告)日：2008-02-28

申请号：US11583805

申请日：2006-10-20

Applicant: Sheng Da Tsai

Inventor： Sheng Da Tsai

IPC: H01L29/00 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10855 ,  H01L28/40

Abstract: A capacitor structure comprises a substrate having a contact plug, a conductive cylinder positioned on the substrate and an electroplating structure covering the conductive cylinder, wherein a bottom electrode of the capacitor structure comprises the conductive cylinder and the electroplating structure. The conductive cylinder can be a hollow conductive cylinder, and the electroplating structure comprises a first conductive layer covering the inner sidewall and bottom surface of the hollow conductive cylinder and a second conductive layer covering the first conductive layer and the outer sidewall of the hollow conductive cylinder. The conductive cylinder and the electroplating structure can be made of different conductive material, and the free end of the conductive cylinder is preferably round. The conductive cylinder can be made of titanium nitride or tantalum nitride, while the electroplating structure can be made of ruthenium or platinum.

Abstract translation: 电容器结构包括具有接触插塞的基板，位于基板上的导电圆柱体和覆盖导电圆柱体的电镀结构，其中电容器结构的底部电极包括导电圆柱体和电镀结构。 导电圆柱体可以是中空导电圆柱体，并且电镀结构包括覆盖中空导电圆柱体的内侧壁和底表面的第一导电层和覆盖中空导电圆柱体的第一导电层和外侧壁的第二导电层 。 导电圆柱体和电镀结构可以由不同的导电材料制成，并且导电圆筒的自由端优选为圆形。 导电圆柱体可由氮化钛或氮化钽制成，而电镀结构可由钌或铂制成。

公开(公告)号：US20080042117A1

公开(公告)日：2008-02-21

申请号：US11558880

申请日：2006-11-10

Applicant: Hong-Hui Hsu

Inventor： Hong-Hui Hsu

IPC: H01L29/04

CPC classification number: H01L45/144 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1675

Abstract: A phase-change memory and fabrication method thereof are disclosed. The phase-change memory comprises a first dielectric layer with a first opening formed on a substrate. A first electrode is filled into the first opening. A second dielectric pillar is formed on the first electrode. A first conducting layer is formed on the sidewalls of the second dielectric pillar, electrically connecting the first electrode. A third dielectric layer is formed on the substrate, exposing the top surface of the first conducting layer. A phase-change layer is formed on the third dielectric layer and directly contacts the top surface of the first conducting layer. A fourth dielectric layer, having a second opening exposing the top surface of the phase-change layer, is formed on the substrate. A second conducting layer is filled into the second opening, electrically connecting to a second electrode.

Abstract translation: 公开了一种相变存储器及其制造方法。 相变存储器包括在基板上形成有第一开口的第一电介质层。 第一电极被填充到第一开口中。 第二电介质柱形成在第一电极上。 第一导电层形成在第二介电柱的侧壁上，电连接第一电极。 第三电介质层形成在衬底上，露出第一导电层的顶表面。 相变层形成在第三电介质层上，并且直接接触第一导电层的顶表面。 在基板上形成具有暴露相变层顶表面的第二开口的第四绝缘层。 第二导电层被填充到第二开口中，电连接到第二电极。

公开(公告)号：US07332396B2

公开(公告)日：2008-02-19

申请号：US11456381

申请日：2006-07-10

Applicant: Jim Lin ,  San-Jung Chang ,  Yu-Cheng Lo

Inventor： Jim Lin ,  San-Jung Chang ,  Yu-Cheng Lo

IPC: H01L21/8242 ,  H01L21/336

CPC classification number: H01L29/42376 ,  H01L21/28238 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7834

Abstract: A semiconductor device with a recessed channel and a method of fabricating the same are provided. The semiconductor device comprises a substrate, a gate, a source, a drain, and a reverse spacer. The substrate comprises a recessed trench. The gate is formed above the recessed trench and extends above the substrate. The gate further comprises a polysilicon layer and a conductive layer; wherein the polysilicon layer is formed inside the recessed trench of the substrate, and the conductive layer is formed above the polysilicon layer and extends above the substrate. Moreover, the width of the conductive layer increases gradually bottom-up. The source and the drain are formed respectively at two sides of the gate. The reverse spacer is formed above the polysilicon layer and against the sidewall of the conductive layer.

Abstract translation: 提供具有凹槽的半导体器件及其制造方法。 半导体器件包括衬底，栅极，源极，漏极和反向间隔物。 衬底包括凹槽。 栅极形成在凹槽的上方并在衬底上方延伸。 栅极还包括多晶硅层和导电层; 其中所述多晶硅层形成在所述衬底的所述凹槽内，并且所述导电层形成在所述多晶硅层上方并在所述衬底上方延伸。 此外，导电层的宽度自底向上增加。 源极和漏极分别形成在栅极的两侧。 反向间隔物形成在多晶硅层上方并抵靠导电层的侧壁上。

公开(公告)号：US07323729B2

公开(公告)日：2008-01-29

申请号：US11431087

申请日：2006-05-04

Applicant: Zhong Dong ,  Chuck Jang ,  Chia-Shun Hsiao

Inventor： Zhong Dong ,  Chuck Jang ,  Chia-Shun Hsiao

IPC: H01L29/76

CPC classification number: H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28158 ,  H01L21/3105 ,  H01L21/31612

Abstract: A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as N2O. In one embodiment, a DCS-HTO film is annealed by heating N2O gas to a temperature in the range of about 825° C. to about 950° C. so as to trigger exothermic decomposition of the N2O gas and flowing the heated gas across the DCS-HTO film so that disassociated atomic oxygen radicals within the heated N2O gas can transfer disassociating energy to chlorine atoms bound within the DCS-HTO film and so that the atomic oxygen radicals can fill oxygen vacancies within the semiconductor-oxide matrix of DCS-HTO film. An improved ONO structure may be formed with the annealed DCS-HTO film for use in floating gate or other memory applications.

Abstract translation: 公开了一种方法和装置，用于降低通过化学气相沉积（CVD）形成的半导体氧化物组合物中的氯和/或其它结合的污染物的浓度，所述半导体氧化物组合物使用提供半导体元素的反应物如二氯硅烷（DCS）和氧 提供反应物如N 2 O。 在一个实施方案中，通过将N 2 O 2气体加热至约825℃至约950℃的温度来退火DCS-HTO膜，以引发放热分解 N 2 O气体并使加热的气体流过DCS-HTO膜，使得加热的N 2 O气体内的解离的原子氧自由基能够将分解能量转移到结合的氯原子上 在DCS-HTO膜内，使得原子氧自由基可以填充DCS-HTO膜的半导体氧化物基质内的氧空位。 可以用退火的DCS-HTO膜形成改进的ONO结构，用于浮动栅极或其他存储器应用中。

公开(公告)号：US20080020293A1

公开(公告)日：2008-01-24

申请号：US11529496

申请日：2006-09-29

Applicant: Yee Kai Lai

Inventor： Yee Kai Lai

IPC: G03C5/00 ,  G03F1/00

CPC classification number: G03F1/28

Abstract: A vortex mask comprises a substrate, a first phase region positioned on the substrate, a second phase region surrounding the first phase region, and a third phase region positioned on the substrate and connected to the first phase region and the second phase region. When exposure beams penetrate the first phase region, the second phase region and the third region of the vortex mask, there will be 90 degrees of phase difference from each other. In addition, the first phase region and the third phase region can be positioned in a mirror image manner, and the third phase region connects to the first phase region and the second phase region in a point manner, which can be used to define the shape of a circular pattern.

Abstract translation: 涡流掩模包括基板，位于基板上的第一相位区域，围绕第一相位区域的第二相位区域和位于基板上并连接到第一相位区域和第二相位区域的第三相位区域。 当曝光光束穿过第一相位区域时，涡流掩模的第二相位区域和第三区域将彼此相差90度。 此外，第一相位区域和第三相位区域可以以镜像方式定位，并且第三相位区域以点的方式连接到第一相位区域和第二相位区域，其可以用于限定形状 的圆形图案。