公开(公告)号：US20230067948A1

公开(公告)日：2023-03-02

申请号：US17540339

申请日：2021-12-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Judson R. Holt

IPC: H01L29/739 ,  H01L29/66

Abstract: Structures for a diode and methods of fabricating a structure for a diode. The structure includes a layer comprised of a semiconductor material. The layer includes a first section, a second section, and a third section laterally positioned between the first section and the second section. The structure includes a first terminal having a raised semiconductor layer on the first section of the layer, a second terminal including a portion on the second section of the layer, and a gate on the third section of the layer.

公开(公告)号：US20230067523A1

公开(公告)日：2023-03-02

申请号：US17456943

申请日：2021-11-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu ,  Alexander M. Derrickson

IPC: H01L29/10 ,  H01L29/735 ,  H01L29/66

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.

公开(公告)号：US20230067304A1

公开(公告)日：2023-03-02

申请号：US17411122

申请日：2021-08-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Roderick A. Augur

IPC: G02B6/122 ,  G02B6/125 ,  G02B6/136

Abstract: Disclosed is a photonic integrated circuit (PIC) structure including: a first waveguide with a first main body and a first end portion, which is tapered; and a second waveguide with a second main body and a second end portion, which has two branch waveguides that are positioned adjacent to opposing sides, respectively, of the first end portion of the first waveguide and that branch out from the second main body, thereby forming a V, U or similar shape. The arrangement of the two branch waveguides of the second end portion of the second waveguide relative to the tapered first end portion of the first waveguide allows for mode matching conditions to be met at multiple locations at the interface between the waveguides, thereby creating multiple signal paths between the waveguides and effectively reducing the light signal power density along any one path to prevent or at least minimize any power-induced damage.

公开(公告)号：US20230066996A1

公开(公告)日：2023-03-02

申请号：US17541603

申请日：2021-12-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander Derrickson

IPC: H01L29/735 ,  H01L29/24 ,  H01L21/02 ,  H01L29/66

Abstract: Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes an emitter and a collector comprised of a first two-dimensional material having a first conductivity type, and an intrinsic base comprised of a second two-dimensional material having a second conductivity type different than the first conductivity type. The intrinsic base is laterally positioned between the emitter and the collector.

公开(公告)号：US11592617B2

公开(公告)日：2023-02-28

申请号：US17193379

申请日：2021-03-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/293 ,  G02B6/125 ,  G02B6/35 ,  F21V8/00 ,  G02B6/136 ,  G02B6/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to non-planar waveguide structures and methods of manufacture. The structure includes: a first waveguide structure; and a non-planar waveguide structure spatially shifted from the first waveguide structure and separated from the first waveguide structure by an insulator material.

公开(公告)号：US11588062B2

公开(公告)日：2023-02-21

申请号：US17065839

申请日：2020-10-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Abdelsalam Aboketaf ,  Yusheng Bian

IPC: H01L31/0352 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/102

Abstract: Structures for a photodetector and methods of fabricating a structure for a photodetector. A photodetector includes a photodetector pad coupled to a waveguide core and a light-absorbing layer coupled to the photodetector pad. The light-absorbing layer has a body, a first taper that projects laterally from the body toward the waveguide core, and a second taper that projects laterally from the body toward the waveguide core. The photodetector pad includes a tapered section that is laterally positioned between the first taper and the second taper of the light-absorbing layer.

公开(公告)号：US11587888B2

公开(公告)日：2023-02-21

申请号：US16713709

申请日：2019-12-13

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Asli Sahin ,  Thomas F. Houghton ,  Jennifer A. Oakley ,  Jeremy S. Alderman ,  Karen A. Nummy ,  Zhuojie Wu

IPC: G02B6/42 ,  H01L23/00 ,  G02B6/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a moisture seal for photonic devices and methods of manufacture. The structure includes: a first trench in at least one substrate material; a guard ring structure with an opening and which at least partially surrounds the first trench; and a second trench at a dicing edge of the substrate, the second trench being lined on sidewalls with barrier material and spacer material over the barrier material.

公开(公告)号：US11585703B2

公开(公告)日：2023-02-21

申请号：US16700358

申请日：2019-12-02

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng-Huat Toh ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: G01K7/01 ,  G11C11/406 ,  G11C11/4072 ,  G11C7/04

Abstract: Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.

公开(公告)号：US11581430B2

公开(公告)日：2023-02-14

申请号：US16548518

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： David Pritchard ,  Heng Yang ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/06 ,  H01L31/00 ,  H01L29/76 ,  H01L29/08 ,  H01L29/10

Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

公开(公告)号：US20230039286A1

公开(公告)日：2023-02-09

申请号：US17394723

申请日：2021-08-05

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Kyong Jin HWANG ,  Milova PAUL ,  Sagar P. Karalkar ,  Robert J. Gauthier, Jr.

IPC: H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure comprising a vertical silicon controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying continuous layer of a second dopant type within a substrate.