公开(公告)号：US20040036999A1

公开(公告)日：2004-02-26

申请号：US10464435

申请日：2003-06-16

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Chrappan Soldavini ,  Roberto Oboe ,  Paolo Capretta

IPC: G11B005/596 ,  G11B021/02

CPC classification number: H02P25/034

Abstract: A method of driving an electrical load having a complex electrical impedance, such as a voice-coil motor controlling the position of a read/write head in a data storage disk drive system, comprises providing a voltage-mode driver generating drive signals for the electrical load in response to drive commands. Compensated commands for the voltage-mode driver are generated filtering the drive commands, compensating for a phase shift between electrical quantities delivered to the electrical load. The voltage-mode drive thus emulates a conventional, but more expensive, current-mode drive. In a preferred embodiment, the method comprises estimating characteristic parameters of the electrical load during the operation, and adapting the filtering to the estimated characteristic parameters. The estimation comprises implementing a Kalman filtering algorithm, particularly an extended Kalman filtering.

Abstract translation: 驱动具有复电阻抗的电负载的方法，例如控制数据存储盘驱动系统中读/写头位置的音圈电机，包括提供电压模式驱动器，产生用于电 响应驱动命令加载。 产生用于电压模式驱动器的补偿命令，对驱动命令进行滤波，补偿传送到电负载的电量之间的相移。 因此，电压模式驱动器模拟常规但是更昂贵的电流模式驱动器。 在优选实施例中，该方法包括估计操作期间的电负载的特征参数，以及使滤波适应估计的特征参数。 估计包括实现卡尔曼滤波算法，特别是扩展卡尔曼滤波。

公开(公告)号：US20040032403A1

公开(公告)日：2004-02-19

申请号：US10445137

申请日：2003-05-23

Applicant: STMicroelectronics S.r.I. and DORA S.p.A.

Inventor： Leonardo Sala ,  Daniele Domanin ,  Roberto Gariboldi

IPC: G09G005/00

CPC classification number: G09G3/3625 ,  G09G3/2018 ,  G09G3/2022 ,  G09G2320/0247 ,  G09G2320/0266

Abstract: The present invention relates to a driving method for flat panel display devices, particularly a driving method combining a Multi Line Addressing (MLA) technique and a Frame Rate Control (FRC) technique, for flat panel display devices such as Liquid Crystal Display (LCD). In an embodiment the method of driving an image display device comprises the following steps: dividing row electrodes of an image device, having a plurality of row electrodes and a plurality of column electrodes, into a plurality of subgroups; selecting one of the plurality of said subgroups having a prefixed number of electrodes; performing a gray scale display by a frame rate control (FRC) by using a prefixed number of frames and a prefixed number of bits representing the gray levels; decomposing one of said frame in a number of time instants proportional to said prefixed number of electrodes; putting the bits representing the gray levels equally distributed in said prefixed number of frames.

Abstract translation: 本发明涉及用于平板显示装置的驱动方法，特别是组合多线寻址（MLA）技术和帧速率控制（FRC）技术的驱动方法，用于诸如液晶显示器（LCD）的平板显示装置， 。 在一个实施例中，驱动图像显示装置的方法包括以下步骤：将具有多个行电极和多个列电极的图像装置的行电极分成多个子组; 选择所述多个所述子组中的一个具有预定数量的电极; 通过使用预定数量的帧和表示灰度级的前缀数目的比特来执行帧速率控制（FRC）的灰度级显示; 在与所述预定数量的电极成比例的多个时刻中分解所述帧中的一个; 将表示灰度级的位平均分配在所述前缀数目的帧中。

公开(公告)号：US20030235013A1

公开(公告)日：2003-12-25

申请号：US10429266

申请日：2003-05-02

Applicant: STMicroelectronics S.r.I.

Inventor： Marco Del Sarto ,  Mauro Marchi ,  Lorenzo Baldo ,  Simone Sassolini

IPC: G11B005/56

CPC classification number: G11B5/4826

Abstract: A read/write assembly for magnetic hard disks includes at least: one supporting element; one read/write (R/W) transducer; one micro-actuator, set between the R/W transducer and the supporting element; one electrical-connection structure for connection to a remote device carried by the supporting element and connected to the R/W transducer and to the micro-actuator. In addition, a protective structure, set so as to cover the micro-actuator is made of a single piece with the electrical-connection structure.

Abstract translation: 用于磁性硬盘的读/写组件至少包括：一个支撑元件; 一个读/写（R / W）传感器; 一个微致动器，设置在R / W换能器和支撑元件之间; 一个电连接结构，用于连接到由支撑元件承载并连接到R / W传感器和微致动器的远程设备。 此外，设置成覆盖微致动器的保护结构由具有电连接结构的单件制成。

公开(公告)号：US20030201503A1

公开(公告)日：2003-10-30

申请号：US10430771

申请日：2003-05-06

Applicant: STMicroelectronics, S.r.I.

Inventor： Ferruccio Frisina

IPC: H01L029/76

CPC classification number: H01L29/7802 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/66712

Abstract: MOS-gated power device including a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type. A plurality of doped regions of a first conductivity type is formed in the semiconductor material layer, each one of the doped regions being disposed under a respective body region and being separated from other doped regions by portions of the semiconductor material layer.

Abstract translation: 包括多个基本功能单元的MOS门控功率器件，每个基本功能单元包括形成在第二导电类型的半导体材料层中的第一导电类型的体区。 在半导体材料层中形成第一导电类型的多个掺杂区域，每个掺杂区域设置在相应的主体区域下方，并且通过半导体材料层的一部分与其它掺杂区域分离。

公开(公告)号：US20030182533A1

公开(公告)日：2003-09-25

申请号：US10371221

申请日：2003-02-21

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Poli ,  Paolino Schillaci ,  Salvatore Polizzi

IPC: G06F012/00 ,  G06F012/14

CPC classification number: G11C16/22

Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

Abstract translation: 本发明提供了一种协议周期，在该协议周期期间，发送存储器地址和要写入的所有数据字节，并且通过在对应于一个存储器区域的存储器扇区中写入第一个字节，对所有发送的数据字节仅执行一次写入处理 通过将所发送的地址的2个最低有效位和连续地址中的所有其他发送字节重置为零而产生的第一地址。 该方法包括在存储器件的存储器阵列中的连续存储器地址中写入一定数量的N个数据字节，并且包括不保护要写入数据的存储器扇区，将编程命令传送到存储器件，与 存储器件将要存储的位并指定要写入的扇区的相对存储器地址，以及将数据位写入存储器。

公开(公告)号：US20030181011A1

公开(公告)日：2003-09-25

申请号：US10351281

申请日：2003-01-24

Applicant: STMicroelectronics S.r.I.

Inventor： Giuseppe Curro ,  Barbara Fazio

IPC: H01L021/336

CPC classification number: H01L29/7813 ,  H01L29/4933

Abstract: A process for forming a trench gate power MOS transistor includes forming an epitaxial layer having a first type of conductivity on a semiconductor substrate, and forming a body region having a second type of conductivity on the epitaxial layer. A gate trench is formed in the body region and in the epitaxial layer. The process further includes countersinking upper portions of the gate trench, and forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof. A gate conducting layer is formed on surfaces of the gate dielectric layer for defining a gate electrode. The gate conducting layer has a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein. The residual cavity is filled with a filler layer. The gate conducting layer is removed from an upper surface of the body region while using the filler layer as a self-aligned mask. The edge surfaces of the gate conducting layer are oxidized. Source regions are formed by implanting dopants in the body region while using the oxidized edge surfaces as a self-aligned mask, and the implanted dopants are diffused in the body region.

Abstract translation: 形成沟槽栅极功率MOS晶体管的工艺包括在半导体衬底上形成具有第一导电类型的外延层，并在外延层上形成具有第二导电类型的体区。 在体区域和外延层中形成栅极沟槽。 该工艺还包括锪孔栅极沟槽的上部，以及在包括其上部的栅极沟槽的表面上形成栅极电介质层。 栅极导电层形成在用于限定栅电极的栅极电介质层的表面上。 栅极导电层的厚度不足以完全填充栅极沟槽，从而残留在其中的空腔。 残留的空腔填充有填料层。 在使用填充层作为自对准掩模的同时，从体区的上表面除去栅极导电层。 栅极导电层的边缘表面被氧化。 源区域通过在使用氧化边缘表面作为自对准掩模的同时在体区中注入掺杂剂而形成，并且注入的掺杂剂在体区中扩散。

公开(公告)号：US20030171004A1

公开(公告)日：2003-09-11

申请号：US10379490

申请日：2003-03-04

Applicant: STMicroelectronics S.r.I.

Inventor： Michele Vulpio

IPC: H01L021/31 ,  C23C016/00

CPC classification number: H01L21/02126 ,  C23C16/30 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/3122 ,  Y10T428/31663

Abstract: A method is for low-dielectric-constant film deposition on a surface of a semiconductor substrate. The deposition may be by chemical vapor deposition (CVD) techniques and may include a wide class of precursor monomeric compounds, namely organosilanes.

Abstract translation: 一种用于半导体衬底表面上的低介电常数膜沉积的方法。 沉积可以通过化学气相沉积（CVD）技术，并且可以包括广泛类型的前体单体化合物，即有机硅烷。

公开(公告)号：US20030149831A1

公开(公告)日：2003-08-07

申请号：US10331177

申请日：2002-12-27

Applicant: STMicroelectronics S.r.I.

Inventor： Emanuele Confalonieri ,  Marco Sforzin

IPC: G06F012/00

CPC classification number: G06F11/1072

Abstract: A decoding structure for a memory device with a control code is used in a memory including a matrix of memory cells grouped into pages to each of which a block of control information is associated, and a plurality of reading elements for reading a plurality of pages in parallel. The decoding structure selectively connects each reading element to a plurality of memory cells, and selectively connects each memory cell to a plurality of reading elements.

Abstract translation: 具有控制码的存储器件的解码结构被用于存储器中的存储器，该存储器包括被分组成一页的存储器单元矩阵，每个存储器单元的一个控制信息块相关联，以及多个用于读取多个页面的读取元件 平行。 解码结构将每个读取元件选择性地连接到多个存储单元，并且将每个存储单元选择性地连接到多个读取元件。

公开(公告)号：US20030146460A1

公开(公告)日：2003-08-07

申请号：US10327704

申请日：2002-12-20

Applicant: STMicroelectronics S.r.I

Inventor： Raffaele Zambrano ,  Cesare Artoni

IPC: G11C007/00 ,  G11C029/00 ,  H01L029/76 ,  H01L029/94 ,  H01L027/108

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75 ,  H01L28/91

Abstract: A memory cell of a stacked type is formed by a MOS transistor and a ferroelectric capacitor. The MOS transistor is formed in an active region of a substrate of semiconductor material and comprises a conductive region. The ferroelectric capacitor is formed on top of the active region and comprises a first and a second electrodes separated by a ferroelectric region. A contact region connects the conductive region of the MOS transistor to the first electrode of the ferroelectric capacitor. The ferroelectric capacitor has a non-planar structure, formed by a horizontal portion and two side portions extending transversely to, and in direct electrical contact with, the horizontal portion.

Abstract translation: 堆叠型存储单元由MOS晶体管和铁电电容器形成。 MOS晶体管形成在半导体材料的衬底的有源区中，并且包括导电区域。 铁电电容器形成在有源区的顶部，并且包括由铁电区域分开的第一和第二电极。 接触区域将MOS晶体管的导电区域与铁电体电容器的第一电极连接。 铁电电容器具有非水平部分形成的非平面结构，该水平部分横向于与水平部分直接电接触延伸的两个侧部。

公开(公告)号：US20030109183A1

公开(公告)日：2003-06-12

申请号：US10243972

申请日：2002-09-12

Applicant: STMicroelectronics S.r.I. ,  Hewlett-Packard Company

Inventor： Ubaldo Mastromatteo ,  Mauro Bombonati ,  Daniela Morin ,  Marta Mottura ,  Mauro Marchi

IPC: H01R009/22

CPC classification number: B81C1/00269 ,  H01L21/185 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13164 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/812 ,  H01L2224/81201 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/013

Abstract: A process for bonding two distinct substrates that integrate microsystems, including the steps of forming micro-integrated devices in at least one of two substrates using micro-electronic processing techniques and bonding the substrates. Bonding is performed by forming on a first substrate bonding regions of deformable material and pressing the substrates one against another so as to deform the bonding regions and to cause them to react chemically with the second substrate. The bonding regions are preferably formed by a thick layer of a material chosen from among aluminum, copper and nickel, covered by a thin layer of a material chosen from between palladium and platinum. Spacing regions ensure exact spacing between the two wafers.