公开(公告)号：US5793085A

公开(公告)日：1998-08-11

申请号：US481928

申请日：1995-06-07

Applicant: Bruno Vajana ,  Emilio Ghio

Inventor： Bruno Vajana ,  Emilio Ghio

IPC: H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/76

CPC classification number: H01L21/8249 ,  H01L21/8248 ,  H01L27/0623

Abstract: A bipolar transistor, comprising a collector region, a base region, and an emitter region, is a type which is compatible to CMOS processes leading to the formation, on a semiconductor substrate, of N-channel and P-channel MOS transistors having respective source and drain regions. In such bipolar transistor, the collector region is a substrate diffused pocket and the base region is formed within the diffused pocket simultaneously with the source and drain regions of the P-channel MOS transistors. Further, the emitter region is incorporated, in turn, to the base region simultaneously with the source and drain regions of the N-channel MOS transistors.

Abstract translation: 包括集电极区域，基极区域和发射极区域的双极晶体管是与CMOS工艺兼容的类型，其导致在半导体衬底上形成具有相应源极的N沟道和P沟道MOS晶体管 和漏区。 在这种双极性晶体管中，集电极区域是衬底扩散的阱，并且基底区域与P沟道MOS晶体管的源极和漏极区域同时形成在扩散的凹穴内。 此外，发射极区域又与N沟道MOS晶体管的源极和漏极区域同时并入基极区域。

公开(公告)号：US5789971A

公开(公告)日：1998-08-04

申请号：US560001

申请日：1995-11-17

Applicant: Paolo Colletti ,  Gregorio Bontempo ,  Francesco Pulvirenti ,  Roberto Gariboldi

Inventor： Paolo Colletti ,  Gregorio Bontempo ,  Francesco Pulvirenti ,  Roberto Gariboldi

IPC: H01L27/04 ,  G05F1/573 ,  H01L21/822 ,  H01L29/78 ,  H02H7/00 ,  H03K17/08 ,  G05F1/10

CPC classification number: G05F1/573

Abstract: A protection circuit for at least one power transistor which has at least one control terminal and two main conduction terminals defining a main conduction path includes a first detection means designed to generate a first electrical signal approximately proportional to current flowing in the main conduction path. Second detection means are designed to generate a second electrical signal approximately proportional to voltage across the main conduction path. Multiplying means receive at input the first and second signals and are designed to generate an electrical product signal substantially corresponding to the product of at least the latter. A generator generates an electrical reference signal, and operational amplifier means receive at input the product signal and the reference signal and are designed to generate an electrical difference signal substantially corresponding to their difference. Control means are designed to drive the control terminal on the basis of the difference signal so that the product signal is not greater than the reference signal.

Abstract translation: 用于至少一个功率晶体管的保护电路，其具有至少一个控制端子和限定主导电路径的两个主导电端子，包括设计成产生与在主导通路径中流动的电流近似成比例的第一电信号的第一检测装置。 第二检测装置被设计成产生与主传导路径上的电压近似成比例的第二电信号。 乘法装置在输入端处接收第一和第二信号，并被设计成产生基本上对应于至少后者的乘积的电产品信号。 发生器产生电参考信号，并且运算放大器装置在输入端接收产品信号和参考信号，并且被设计成产生基本上与其差异相对应的电差信号。 控制装置被设计成基于差分信号驱动控制终端，使得乘积信号不大于参考信号。

公开(公告)号：US5780995A

公开(公告)日：1998-07-14

申请号：US550690

申请日：1995-10-31

Applicant: Giampietro Maggioni ,  Mirco Contucci

Inventor： Giampietro Maggioni ,  Mirco Contucci

IPC: H02J7/16 ,  H01M10/44 ,  H02J7/24 ,  H02J7/14

CPC classification number: H02J7/242 ,  Y02T10/7005

Abstract: A circuit for regulating the charging voltage to a battery and connected to the field inductor (IND) of an alternator (ALT) which supplies that voltage. It is connected by a control cable to the battery and comprises an electric path, extending between a terminal for connection to the alternator and ground, which is only activated when the battery voltage drops below a predetermined threshold value. This electric path comprises a switch (TSW) driven from a control circuit (COMP1,T4) which sense the battery voltage, and when activated, the voltage drop across the path is substantially equal to that of the regulated voltage. The control circuit also senses breakage in the battery sensing cable, and ceases driving the alternator when this occurs.

Abstract translation: 用于调节对电池的充电电压并连接到提供该电压的交流发电机（ALT）的励磁电感器（IND）的电路。 它通过控制电缆连接到电池，并且包括在用于连接到交流发电机的接线端子和接地之间延伸的电路，该电路仅在电池电压低于预定阈值时被激活。 该电路包括从感测电池电压的控制电路（COMP1，T4）驱动的开关（TSW），并且当被激活时，路径上的电压降基本上等于调节电压的电压降。 控制电路还检测电池传感电缆的断裂，并在发生这种情况时停止驱动交流发电机。

公开(公告)号：US5777460A

公开(公告)日：1998-07-07

申请号：US846539

申请日：1997-04-29

Applicant: Cristiano Calligaro ,  Piero Malcovati ,  Guido Torelli

Inventor： Cristiano Calligaro ,  Piero Malcovati ,  Guido Torelli

IPC: G05F1/46 ,  G05F1/613 ,  G11C5/14 ,  G11C7/00

CPC classification number: G05F1/613 ,  G05F1/465 ,  G11C5/147

Abstract: A voltage step-up circuit with regulated output voltage, comprises a voltage divider and a current-absorption circuit connected between the output terminal of the circuit and ground. A control circuit connected to the divider drives the switching of the current-absorption circuit.

Abstract translation: 具有调节输出电压的升压电路包括连接在电路的输出端和地之间的分压器和电流吸收电路。 连接到分压器的控制电路驱动电流吸收电路的切换。

公开(公告)号：US5761222A

公开(公告)日：1998-06-02

申请号：US538161

申请日：1995-10-02

Applicant: Livio Baldi

Inventor： Livio Baldi

IPC: G06F12/16 ,  G06F11/10 ,  G11C11/56 ,  G11C29/00 ,  G11C29/04 ,  G11C16/06

CPC classification number: G06F11/1072 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G06F11/1064 ,  G11C29/00

Abstract: The present invention relates to a memory device and specifically the multilevel type with error check and correction function and having a data input (DI), a data output (DO) and an address input (A1) and being of the type comprising first memory, circuit (DM) designed to be accessed by means of address for containing user data, second memory circuit (EM) for containing error data concerning said user data, a control logic (CL) designed to receive in the writing phase from said address input (A1) and the data input (DI) a writing address and user data respectively and to generate error data and to write, the data in the first circuit (DM) and second circuit (EM) respectively and designed to receive in the reading phase from said address input (AI) a reading address and extract corresponding user data and error data and combine them to correct any errors and supply them to the data output (DO) and characterized in that the second, circuit (EM) is the type designed to be accessed by means of content and, the content for access corresponding to addresses of said first circuit (DM).

Abstract translation: 本发明涉及一种存储装置，特别涉及具有错误检查和校正功能并具有数据输入（DI），数据输出（DO）和地址输入（A1）并且包括第一存储器的类型的多级型， 设计为通过用于包含用户数据的地址访问的电路（DM），用于包含关于所述用户数据的错误数据的第二存储器电路（EM），设计成在写入阶段从所述地址输入（ A1）和数据输入（DI）分别写入地址和用户数据，并产生错误数据并分别写入第一电路（DM）和第二电路（EM）中的数据，并设计为在读取阶段从 所述地址输入（AI）读取地址并提取对应的用户数据和错误数据，并将它们组合以校正任何错误并将其提供给数据输出（DO），其特征在于，第二电路（EM）是被设计为 被mea访问 的内容，以及与所述第一电路（DM）的地址相对应的访问内容。

公开(公告)号：US5760628A

公开(公告)日：1998-06-02

申请号：US657824

申请日：1996-05-31

Applicant: Giuseppe Cantone ,  Aldo Novelli

Inventor： Giuseppe Cantone ,  Aldo Novelli

IPC: H03K5/1532 ,  H03K5/1252 ,  H03H11/26

CPC classification number: H03K5/1252

Abstract: A pulse generator has an input and two outputs at which to respectively generate pulses in relation to different types of signal edges received at the input of the generator. The generator provides two distinct logic circuit blocks of the sequential type, the blocks being mutually independent for generation of the pulses at the two outputs. In this manner it is possible to easily control the characteristics of the pulses. In addition, if two blocks are connected with appropriate and simple logic networks, it is possible in the generation phase to impose conditions between the pulses at the two outputs in a simple manner and with a certain freedom.

Abstract translation: 脉冲发生器具有一个输入端和两个输出端，分别产生与发生器输入端接收的不同类型的信号边沿相关的脉冲。 发生器提供了两种不同的顺序类型的逻辑电路块，这些块是相互独立的，用于在两个输出端产生脉冲。 以这种方式，可以容易地控制脉冲的特性。 另外，如果两个块与适当和简单的逻辑网络连接，则在生成阶段可以以简单的方式并以一定的自由度在两个输出端的脉冲之间施加条件。

公开(公告)号：USRE35806E

公开(公告)日：1998-05-26

申请号：US512904

申请日：1995-08-09

Applicant: Domenico Rossi ,  Andrea Cuomo ,  Giovanni Pietrobon

Inventor： Domenico Rossi ,  Andrea Cuomo ,  Giovanni Pietrobon

IPC: H02P7/00 ,  H03K17/56

CPC classification number: H02P7/04

Abstract: A multipurpose integrated circuit for driving in a switching mode an externally connected load or loads permits implementation of any appropriate supply scheme of the external load or loads through six output terminals thereof and is therefore useful in a large number of applications. The integrated circuit uses six integrated power switching devices provided with respective recirculation diodes and a single externally connected sensing resistor for generating, by means of a customary PWM control loop, a control signal by which means of a logic circuit configurable by .�.programaming.!. .Iadd.programming .Iaddend.permits the generation of driving signals as a function of the control signal for all six integrated power switches in accordance with a configuration of the driving signals which conforms with the particular scheme of connection of the load or loads selected among the different bridge type and unipolar-motor type schemes which may be selected by programming. A multiplexer is used for selecting among bridge type driving signals and unipolar-motor type driving modes and a ROM provided with two input registers for selecting the specific driving scheme and for regulation, respectively.

Abstract translation: 用于以开关模式驱动外部连接的负载或负载的多用途集成电路允许通过其六个输出端子实现外部负载或负载的任何适当供应方案，因此在大量应用中是有用的。 该集成电路使用六个集成的功率开关器件，它们具有各自的再循环二极管和一个外部连接的感测电阻器，用于通过常规的PWM控制环路产生一个控制信号，通过该控制信号可以通过[程序设计]编程允许 根据与不同桥型和单极电机之间选择的负载或负载的特定连接方案的驱动信号的配置，产生作为所有六个集成电力开关的控制信号的驱动信号的驱动信号 可以通过编程来选择类型方案。 多路复用器用于选择桥式驱动信号和单极电机类型驱动模式，以及一个ROM，分别具有两个输入寄存器，用于选择具体的驱动方案和调节。

公开(公告)号：US5758167A

公开(公告)日：1998-05-26

申请号：US535344

申请日：1995-09-28

Applicant: Roberto Bonetti

Inventor： Roberto Bonetti

IPC: G06F13/24 ,  G06F13/26 ,  G06F9/46

CPC classification number: G06F13/24

Abstract: A management unit for microcontrollers equipped with a decoder for a plurality of interrupt channels, the unit being connected to a central processing unit of the microcontroller to decode and transfer thereto a single interrupt digital signal through the decoder, and comprises a first circuit portion for selecting homolog pairs of channels incorporating a modular chain of elements, each having a respective channel pair connected thereto. The first or selection portion is associated with a second decoding circuit portion, and the interrupt signal is a reform of the channel interrupt vector carrying higher priority in the channel pair selected by the chain.

Abstract translation: 一种用于微控制器的管理单元，其配备有用于多个中断通道的解码器，该单元连接到微控制器的中央处理单元，以通过解码器对单个中断数字信号进行解码和传送，并且包括用于选择的第一电路部分 包含元件链的同构对通道，每个通道具有连接到其上的相应通道对。 第一或选择部分与第二解码电路部分相关联，并且中断信号是在链路选择的信道对中承载较高优先级的信道中断向量的改进。

公开(公告)号：US5757719A

公开(公告)日：1998-05-26

申请号：US869208

申请日：1997-06-05

Applicant: Cristiano Calligaro ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Paolo Cappelletti ,  Guido Torelli

Inventor： Cristiano Calligaro ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Paolo Cappelletti ,  Guido Torelli

IPC: G11C16/02 ,  G11C11/56 ,  G11C13/00

CPC classification number: G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632 ,  G11C2211/5634

Abstract: A page-mode semiconductor memory device comprises a matrix of memory cells arranged in rows and columns, each row forming a memory page of the memory device and comprising at least one group of memory cells, memory page selection means for selecting a row of the matrix, and a plurality of sensing circuits each one associated with a respective column of the matrix. The memory cells are multiple-level memory cells which can be programmed in a plurality of c=2b(b>1) programming states to store b information bits, and the sensing circuits are serial-dichotomic sensing circuits capable of determining, in a number b of consecutive approximation steps, the b information bits stored in the memory cells, at each step one of said b information bits being determined, said at least one group of memory cells of a row forming a number b of memory words of a memory page.

Abstract translation: 页模式半导体存储器件包括以行和列排列的存储器单元矩阵，每行形成存储器件的存储器页，并且包括至少一组存储器单元，存储器页选择装置，用于选择矩阵的一行 ，以及多个感测电路，每个感测电路与矩阵的相应列相关联。 存储器单元是可以以多个c = 2b（b> 1）编程状态编程以存储b个信息位的多级存储器单元，并且感测电路是能够以数字确定的串行二分感测电路 b个连续近似步骤，存储在存储器单元中的b个信息位，在所确定的所述b个信息位的每个步骤中，所述至少一组形成存储器页的存储器字数b的存储单元组 。

公开(公告)号：US5736880A

公开(公告)日：1998-04-07

申请号：US576882

申请日：1995-12-21

Applicant: Melchiorre Bruccoleri ,  Gaetano Cosentino ,  Marco Demicheli ,  Giuseppe Patti

Inventor： Melchiorre Bruccoleri ,  Gaetano Cosentino ,  Marco Demicheli ,  Giuseppe Patti

IPC: H03L7/093 ,  H03L7/089 ,  H03L7/06

CPC classification number: H03L7/0896

Abstract: A differential charge pump circuit employing a lowpass filter network which is chargeable and dischargeable by switchingly controlled current generators. The differential charge pump employs two identical current generators for injecting the same current I in a substantially continuous manner, on the two significant nodes of the lowpass filter. The differential charge pump also employs two pairs of identical, switchingly controlled current generators connected to the two significant nodes, respectively, each capable of pulling a current I. The two generators forming each of the two pairs of switchingly controlled current generators are controlled by one of a pair of control signals (UP, DOWN) and by the inverted signal of the other of the pair of control signals, respectively. All four switchingly controlled generators may be of the same type (N-type), thus ensuring high speed and precision. The two identical (P-type) current generators employed for continuously injecting the same current I on the two nodes of the lowpass filter may be controlled through a common mode feedback loop for enhanced precision.

Abstract translation: 采用低通滤波器网络的差分电荷泵电路，该低通滤波器网络可由切换控制的电流发生器进行充电和放电。 差分电荷泵采用两个相同的电流发生器，以基本上连续的方式在低通滤波器的两个重要节点上注入相同的电流I。 差分电荷泵还采用两对相同的交换控制电流发生器，分别连接到两个有效节点，每个有效节点能够拉电流I.形成两对开关控制电流发生器中的每一对的两个发电机由一个 一对控制信号（UP，DOWN）和另一对控制信号的反相信号。 所有四个交流控制发电机可以是相同类型（N型），从而确保高速度和精度。 用于在低通滤波器的两个节点上连续注入相同电流I的两个相同（P型）电流发生器可以通过共模反馈回路来控制，以提高精度。