公开(公告)号：US20230402745A1

公开(公告)日：2023-12-14

申请号：US18205729

申请日：2023-06-05

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Florian PERMINJAT ,  Karine SAXOD

IPC: H01Q1/38 ,  H01Q1/36 ,  H01Q21/06

CPC classification number: H01Q1/38 ,  H01Q1/364 ,  H01Q21/061

Abstract: An electronic device integrates an antenna. To fabricate such an electronic device, first antenna elements are formed on a first surface of a first substrate. The first substrate is then diced to form antenna chips. Each antenna chip includes, on a first surface corresponding to the first surface of the first substrate, one of the first antenna elements. One of the antenna chips is then bonded onto a transfer substrate. This bonding is made between a second surface of the antenna chip, orthogonal to its first surface, and an upper surface of the transfer substrate.

公开(公告)号：US20230385593A1

公开(公告)日：2023-11-30

申请号：US18316964

申请日：2023-05-12

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Franck Montaudon ,  Julien Goulier

IPC: G06K19/077

CPC classification number: G06K19/07773

Abstract: In an embodiment an electronic device includes a first electronic circuit having a capacitive element with a variable capacitance, wherein the first electronic circuit is configured to couple the capacitive element to an antenna, to measure, by successive iterations, a first analog signal representative of a variation of an instantaneous electric power received by the antenna or representative of the instantaneous electric power received by the antenna and to modify the capacitance of the capacitive element until an amplitude of the instantaneous electric power received by the antenna is a maximum, wherein the antenna is configured to capture an amplitude-modulated electromagnetic field.

公开(公告)号：US20230327666A1

公开(公告)日：2023-10-12

申请号：US18191491

申请日：2023-03-28

Applicant: STMicroelectronics (Grenoble) 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Matthieu Desvergne ,  Marc Sabut ,  Emmanuel Allier ,  Thierry Masson

IPC: H03K17/687 ,  H03K17/22 ,  H03K17/10

CPC classification number: H03K17/6871 ,  H03K17/223 ,  H03K17/102

Abstract: In an embodiment a switch includes a first MOS transistor having its source connected to its channel-forming region and coupled with a first terminal of the switch, its drain coupled with a second terminal of the switch, and its gate connected to a first node of the switch, a diode coupling the first terminal with the first node, a capacitive element coupling a third terminal of the switch with the first node, the third terminal being configured to receive a control signal for the switch and a discharge circuit coupling the first node with the first terminal, the discharge circuit configured to conduct only when a voltage between the first node and the first terminal is greater than or equal to a threshold.

公开(公告)号：US20230302683A1

公开(公告)日：2023-09-28

申请号：US18124834

申请日：2023-03-22

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Research & Development) Limited

Inventor： Melodie CHAPERON ,  William HALLIDAY ,  Jean GAGNIEUX

IPC: B28D5/00 ,  B28D5/04

CPC classification number: B28D5/0082 ,  B28D5/04 ,  B28D5/0052

Abstract: In a method, substrate elements are provided wherein each substrate element has a first side and a second side meeting at a corner point. The substrate elements are picked and then placed on a support device in alignment. A cutting operation is then performed where each of the substrates elements are cut along a cut line having a common first direction which intersects the first and second sides of each of the substrate elements in order to create a third side on each substrate element. The third side of each of the substrate elements meets the first and the second sides at corresponding corner points.

公开(公告)号：US11764731B2

公开(公告)日：2023-09-19

申请号：US18059812

申请日：2022-11-29

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： Benoit Marchand ,  Hamilton Emmanuel Querino De Carvalho ,  Achraf Dhayni ,  Daniele Mangano

IPC: H04B1/04 ,  H03F3/24 ,  H03B5/36 ,  H03L1/02 ,  H03L7/099 ,  G06F1/10

CPC classification number: H03B5/36 ,  G06F1/10 ,  H03F3/245 ,  H04B1/0475 ,  H03B2200/004 ,  H03F2200/451 ,  H04B2001/0408

Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.

公开(公告)号：US20230273896A1

公开(公告)日：2023-08-31

申请号：US18310864

申请日：2023-05-02

Applicant: STMicroelectronics (Grenoble 2)SAS

Inventor： Arnaud Dehamel

IPC: G06F13/42 ,  G06F9/4401 ,  G06F11/30 ,  G06F9/54

CPC classification number: G06F13/4295 ,  G06F9/4418 ,  G06F13/4291 ,  G06F11/3058 ,  G06F9/546

Abstract: The present disclosure relates to a method comprising receiving edges conveyed by a serial bus and separated by multiples of a same duration, determining a measurement value of a ratio between a cycle time of a clock and the duration, and sending bits on the serial bus using the measurement value.

公开(公告)号：US11742755B2

公开(公告)日：2023-08-29

申请号：US17388591

申请日：2021-07-29

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Chesneau

IPC: H02M3/158

CPC classification number: H02M3/158

Abstract: An embodiment voltage converter includes a first transistor and a second transistor coupled in series, and a first circuit configured to control the first and second transistors. The control terminal of the second transistor is coupled to a first output of the first circuit by a second circuit configured to delay the control signals supplied at the first output by a first duration. The control terminal of the first transistor is coupled to a second output of the first circuit by a circuit configured to delay the control signals supplied at the second output, for a second period of each operating cycle, by a duration equal to twice the first duration and, during a second period of each operating cycle, by a duration equal to the first duration.

公开(公告)号：US20230243940A1

公开(公告)日：2023-08-03

申请号：US18126165

申请日：2023-03-24

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Pascal MELLOT

IPC: G01S7/4914 ,  G01S17/36 ,  H01L31/107 ,  G01S7/4865

CPC classification number: G01S7/4914 ,  G01S17/36 ,  H01L31/107 ,  G01S7/4865

Abstract: Described herein is a time-of-flight ranging system and methods for its operation. The system includes an array of single photon avalanche diode (SPAD) pixels and control circuitry. The control circuitry simultaneously accumulates integrated SPAD event data from one cluster of SPAD pixels while integrating SPAD event data from another cluster during different target illuminations. The system also includes first and second VCSEL clusters, each responsible for a different target illumination. By processing and managing the data in this manner, the system can effectively reduce the time used to gather and analyze the event data, leading to faster and more accurate distance measurements.

公开(公告)号：US11710976B2

公开(公告)日：2023-07-25

申请号：US17187478

申请日：2021-02-26

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Alexandre Pons ,  Jean Camiolo ,  Meriem Mersel

IPC: H02J7/00 ,  H02M1/08

CPC classification number: H02J7/00712 ,  H02J7/007192 ,  H02J2207/20 ,  H02J2207/30

Abstract: An embodiment of the present disclosure relates to a power supply interface comprising: a converter delivering a first DC voltage; a resistor connected between the converter and an output terminal of the interface delivering a second DC voltage; a first circuit delivering a second signal representative of a difference between the second DC voltage and a voltage threshold when a first signal is in a first state, and at a default value otherwise; a second circuit delivering a third signal representative of a value of a current in first resistor multiplied by a gain of the third circuit, and modifying the gain based on the second signal; and a third circuit configured to deliver a signal for controlling the converter based at least on the third signal.

公开(公告)号：US20230223277A1

公开(公告)日：2023-07-13

申请号：US18094775

申请日：2023-01-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Fanny LAPORTE ,  Ludovic FOURNEAUD ,  Eric SAUGIER

IPC: H01L21/48 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/48

Abstract: An integrated circuit chip carrier includes a wall surrounding a cavity. The wall includes one or more levels where each level is formed from a layer of a resin around a block. The block is made of a material different from the resin. The block is removed to open the cavity.