公开(公告)号：US11751482B2

公开(公告)日：2023-09-05

申请号：US17980529

申请日：2022-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Chin-Yang Hsieh

IPC: H01L27/22 ,  H10N50/01 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

公开(公告)号：US11749748B2

公开(公告)日：2023-09-05

申请号：US17367647

申请日：2021-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

公开(公告)号：US20230270017A1

公开(公告)日：2023-08-24

申请号：US17703967

申请日：2022-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Yi Wu ,  Jia-Rong Wu ,  Yu-Hsiang Lin ,  Yi-Wen Chen ,  Kun-Sheng Yang

IPC: H01L43/12 ,  H01L21/308

CPC classification number: H01L43/12 ,  H01L21/308

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the MTJ and the SOT layer, forming a first hard mask on the IMD layer, forming a semiconductor layer on the first hard mask, and then patterning the first hard mask.

公开(公告)号：US20230268397A1

公开(公告)日：2023-08-24

申请号：US18135206

申请日：2023-04-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yu-Chi Wang ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/15 ,  H01L29/778

CPC classification number: H01L29/151 ,  H01L29/7786

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

公开(公告)号：US20230268246A1

公开(公告)日：2023-08-24

申请号：US18136329

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Purakh Raj Verma ,  Ching-Yang Wen ,  Chee Hau Ng

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/3735 ,  H01L21/4871 ,  H01L23/15 ,  H01L23/3736

Abstract: A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

公开(公告)号：US11737285B2

公开(公告)日：2023-08-22

申请号：US17202296

申请日：2021-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hui-Lin Wang ,  Kun-I Chou ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H10B61/00 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/80

Abstract: A memory array includes at least one strap region having therein a plurality of source line straps and a plurality of word line straps, and at least two sub-arrays having a plurality of staggered, active magnetic storage elements. The at least two sub-arrays are separated by the strap region. A plurality of staggered, dummy magnetic storage elements is disposed within the strap region.

公开(公告)号：US11737265B2

公开(公告)日：2023-08-22

申请号：US17888511

申请日：2022-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Hung-Hsun Shuai

IPC: H01L21/00 ,  H10B41/30 ,  H10B41/10 ,  H10B43/10 ,  H10B43/30

CPC classification number: H10B41/30 ,  H10B41/10 ,  H10B43/10 ,  H10B43/30

Abstract: A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.

公开(公告)号：US11735644B2

公开(公告)日：2023-08-22

申请号：US17551149

申请日：2021-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou ,  Chih-Tung Yeh

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/308 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L21/3081 ,  H01L29/7787 ,  H01L29/2003 ,  H01L29/205

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

公开(公告)号：US20230262993A1

公开(公告)日：2023-08-17

申请号：US18304335

申请日：2023-04-20

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yi Lin ,  Tang Chun Weng ,  Chia-Chang Hsu ,  Yung Shen Chen ,  Chia-Hung Lin

IPC: H10B61/00 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H01L23/5226 ,  H01L23/5283 ,  H10N50/01 ,  H10N50/80

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

公开(公告)号：US20230261108A1

公开(公告)日：2023-08-17

申请号：US18305383

申请日：2023-04-24

Applicant: United Microelectronics Corp.

Inventor： Chun-Ya Chiu ,  Chih-Kai Hsu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L29/66 ,  H01L29/267

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L21/02532 ,  H01L29/66636 ,  H01L21/02521 ,  H01L29/267

Abstract: The disclosure discloses a manufacturing method for high-voltage transistor. The manufacturing method comprises: providing a substrate; forming a recess in the substrate; forming an epitaxial doped structure with a first conductivity type in the recess of the substrate, wherein a top portion of the epitaxial doped structure comprises a top undoped epitaxial layer; forming a gate structure on the substrate and at least overlapping with the top undoped epitaxial layer; and forming a source/drain region with a second conductivity type in the epitaxial doped structure on a side of the gate structure. The first conductivity type is different from the second conductivity type.