公开(公告)号：US11361827B2

公开(公告)日：2022-06-14

申请号：US17084244

申请日：2020-10-29

Applicant: Micron Technology, Inc.

Inventor： Akira Goda

IPC: G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  G11C16/10 ,  G11C16/04

Abstract: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

公开(公告)号：US11211126B2

公开(公告)日：2021-12-28

申请号：US17027425

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/34 ,  G11C16/12 ,  G11C16/14 ,  G11C16/06 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

公开(公告)号：US20210335817A1

公开(公告)日：2021-10-28

申请号：US17369605

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Byeung Chul Kim ,  Akira Goda

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US20210200461A1

公开(公告)日：2021-07-01

申请号：US17079048

申请日：2020-10-23

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mark A. Helm ,  Giuseppina Puzzilli ,  Peter Feeley ,  Yifen Liu ,  Violante Moschiano ,  Akira Goda ,  Sampath K. Ratnam

IPC: G06F3/06

Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

公开(公告)号：US20210125669A1

公开(公告)日：2021-04-29

申请号：US17080553

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/10 ,  H01L27/115 ,  H01L49/02 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US10985251B2

公开(公告)日：2021-04-20

申请号：US16871600

申请日：2020-05-11

Applicant: Micron Technology, Inc.

Inventor： Minsoo Lee ,  Akira Goda

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/764 ,  H01L29/788 ,  H01L29/423 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.

公开(公告)号：US20210043259A1

公开(公告)日：2021-02-11

申请号：US17084244

申请日：2020-10-29

Applicant: Micron Technology, Inc.

Inventor： Akira Goda

IPC: G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  G11C16/10 ,  G11C16/04

Abstract: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

公开(公告)号：US10833099B2

公开(公告)日：2020-11-10

申请号：US16419736

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L21/02 ,  H01L27/11582 ,  G11C16/14 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11529 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

公开(公告)号：US20200279928A1

公开(公告)日：2020-09-03

申请号：US16871600

申请日：2020-05-11

Applicant: Micron Technology, Inc.

Inventor： Minsoo Lee ,  Akira Goda

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/764 ,  H01L29/788 ,  H01L29/423 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.

公开(公告)号：US20200152271A1

公开(公告)日：2020-05-14

申请号：US16744675

申请日：2020-01-16

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui ,  Akira Goda ,  Peter Sean Feeley

IPC: G11C16/04 ,  G11C16/16 ,  G11C16/10 ,  G11C16/08

Abstract: Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.