公开(公告)号：US08232143B2

公开(公告)日：2012-07-31

申请号：US13171112

申请日：2011-06-28

Applicant: Gary Yama

Inventor： Gary Yama

IPC: H01L21/44

CPC classification number: B81C1/00595 ,  B81C2201/0132 ,  B81C2201/014 ,  H01L21/0475

Abstract: A method of etching a device in one embodiment includes providing a silicon carbide substrate, forming a silicon nitride layer on a surface of the silicon carbide substrate, forming a silicon carbide layer on a surface of the silicon nitride layer, forming a silicon dioxide layer on a surface of the silicon carbide layer, forming a photoresist mask on a surface of the silicon dioxide layer, and etching the silicon dioxide layer through the photoresist mask.

Abstract translation: 在一个实施例中蚀刻器件的方法包括提供碳化硅衬底，在碳化硅衬底的表面上形成氮化硅层，在氮化硅层的表面上形成碳化硅层，在二氧化硅层上形成二氧化硅层 碳化硅层的表面，在二氧化硅层的表面上形成光致抗蚀剂掩模，并且通过光致抗蚀剂掩模蚀刻二氧化硅层。

公开(公告)号：US20120133002A1

公开(公告)日：2012-05-31

申请号：US13298571

申请日：2011-11-17

Applicant: Jochen REINMUTH ,  Heiko Stahl

Inventor： Jochen REINMUTH ,  Heiko Stahl

IPC: H01L29/84 ,  H01L21/00

CPC classification number: B81C1/00571 ,  B81B2203/0118 ,  B81B2203/0136 ,  B81C2201/014

Abstract: A method for producing microelectromechanical structures in a substrate includes: arranging at least one metal-plated layer on a main surface of the substrate in a structure pattern; leaving substrate webs open beneath a structure pattern region by introducing first trenches into the substrate perpendicular to a surface normal of the main surface in a region surrounding the structure pattern; coating the walls of the first trenches perpendicular to the surface normal of the main surface with a passivation layer; and introducing cavity structures into the substrate at the base of the first trenches in a region beneath the structure pattern region.

Abstract translation: 在基板中制造微机电结构的方法包括：以结构图案在基板的主表面上布置至少一个金属镀层; 通过在围绕结构图案的区域中垂直于主表面的表面法垂直地将第一沟槽引入到衬底中，使衬底腹板打开在结构图案区域下方; 用钝化层涂覆垂直于主表面的法线的第一沟槽的壁; 以及在结构图案区域下方的区域中在第一沟槽的基部处将空腔结构引入衬底。

公开(公告)号：US20110290022A1

公开(公告)日：2011-12-01

申请号：US13177485

申请日：2011-07-06

Applicant: Jong Woon Kim ,  Won Kyu Jeung

Inventor： Jong Woon Kim ,  Won Kyu Jeung

IPC: G01P15/02 ,  C23F1/02

CPC classification number: B81C1/00158 ,  B81B3/0062 ,  B81B3/007 ,  B81B2201/0235 ,  B81B2203/053 ,  B81C1/00484 ,  B81C1/00531 ,  B81C1/00539 ,  B81C1/00571 ,  B81C2201/01 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014 ,  C09K13/00 ,  C09K13/08 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/0922 ,  G01P15/18 ,  G01P2015/084 ,  G01P2015/0871

Abstract: Disclosed herein an inertial sensor and a method of manufacturing the same. An inertial sensor 100 according to a preferred embodiment of the present invention is configured to include a plate-shaped membrane 110, a mass body 120 that includes an adhesive part 123 disposed under a central portion 113 of the membrane 110 and provided at the central portion thereof and a patterning part 125 provided at an outer side of the adhesive part 123 and patterned to vertically penetrate therethrough, and a first adhesive layer 130 that is formed between the membrane 110 and the adhesive part 123 and is provided at an inner side of the patterning part 125. An area of the first adhesive layer 130 is narrow by isotropic etching using the patterning part 125 as a mask, thereby making it possible to improve sensitivity of the inertial sensor 100.

Abstract translation: 本文公开了一种惯性传感器及其制造方法。 根据本发明的优选实施例的惯性传感器100被配置为包括板状膜110，质量体120，其包括设置在膜110的中心部分113下方并设置在中心部分处的粘合部123 以及设置在粘合部123的外侧并被图案化以垂直贯穿其中的图案形成部分125，以及形成在膜110和粘合部123之间的第一粘合层130，并且设置在第一粘合层130的内侧 图形部分125.通过使用图案形成部分125作为掩模的各向同性蚀刻，第一粘合剂层130的区域变窄，从而可以提高惯性传感器100的灵敏度。

公开(公告)号：US08064124B2

公开(公告)日：2011-11-22

申请号：US12128469

申请日：2008-05-28

Applicant: Wonsuk Chung ,  Steve Zee ,  Teruo Sasagawa

Inventor： Wonsuk Chung ,  Steve Zee ,  Teruo Sasagawa

IPC: G02B26/00

CPC classification number: B81C1/00801 ,  B81B2201/047 ,  B81C2201/014 ,  G02B26/001 ,  Y10T428/31678

Abstract: The fabrication of a MEMS device such as an interferometric modulator is improved by employing an etch stop layer between a sacrificial layer and a an electrode. The etch stop may reduce undesirable over-etching of the sacrificial layer and the electrode. The etch stop layer may also serve as a barrier layer, buffer layer, and/or template layer. The etch stop layer may include silicon-rich silicon nitride.

Abstract translation: 通过在牺牲层和电极之间采用蚀刻停止层来改善诸如干涉式调制器之类的MEMS器件的制造。 蚀刻停止可以减少对牺牲层和电极的不希望的过蚀刻。 蚀刻停止层也可以用作阻挡层，缓冲层和/或模板层。 蚀刻停止层可以包括富硅的氮化硅。

公开(公告)号：US20110084344A1

公开(公告)日：2011-04-14

申请号：US12579395

申请日：2009-10-14

Applicant: Chien-Hsin Huang ,  Bang-Chiang Lan ,  Ming-I Wang ,  Hui-Min Wu ,  Tzung-I Su ,  Chao-An Su ,  Tzung-Han Tan ,  Min Chen ,  Meng-Jia Lin

Inventor： Chien-Hsin Huang ,  Bang-Chiang Lan ,  Ming-I Wang ,  Hui-Min Wu ,  Tzung-I Su ,  Chao-An Su ,  Tzung-Han Tan ,  Min Chen ,  Meng-Jia Lin

IPC: H01L29/84 ,  H01L21/30

CPC classification number: B81C1/00801 ,  B81B2201/0257 ,  B81B2207/015 ,  B81C2201/014 ,  B81C2203/0735

Abstract: A method of fabricating MEMS device includes: providing a substrate with a first surface and a second surface. The substrate includes at least one logic region and at least one MEMS region. The logic region includes at least one logic device positioned on the first surface of the substrate. Then, an interlayer material is formed on the first surface of the substrate within the MEMS region. Finally, the second surface of the substrate within the MEMS region is patterned. After the pattern process, a vent pattern is formed in the second surface of the substrate within the MEMS region. The interlayer material does not react with halogen radicals. Therefore, during the formation of the vent pattern, the substrate is protected by the interlayer material and the substrate can be prevented from forming any undercut.

Abstract translation: 一种制造MEMS器件的方法包括：向基片提供第一表面和第二表面。 衬底包括至少一个逻辑区域和至少一个MEMS区域。 逻辑区域包括位于衬底的第一表面上的至少一个逻辑器件。 然后，在MEMS区域内的衬底的第一表面上形成中间层材料。 最后，对MEMS区域内的衬底的第二表面进行图案化。 在图案处理之后，在MEMS区域内的衬底的第二表面中形成通气图案。 中间层材料不与卤素原子反应。 因此，在形成通气图案的过程中，基板被中间层材料保护，并且可以防止基板形成任何底切。

公开(公告)号：US07923345B2

公开(公告)日：2011-04-12

申请号：US12158988

申请日：2006-12-18

Applicant: Jan Sonsky ,  Wibo D. Van Noort

Inventor： Jan Sonsky ,  Wibo D. Van Noort

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76229 ,  B81C1/00158 ,  B81C2201/014

Abstract: A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to provide an underetched structure. Access trenches (4) and support trenches (5) are formed in the layered structure through the thickness of the semiconductor layer (9) and through the upper etch stop layer (8). The support trenches extend deeper through the sacrificial layer (12) and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity (30) and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.

Abstract translation: 一种制造半导体器件的方法，其中包括牺牲层的层压结构被夹在两个蚀刻停止层（8,11）之间，并且将半导体膜（9）与体基板（1）分离，以提供未刻划的结构 。 通过半导体层（9）的厚度和通过上蚀刻停止层（8）在层状结构中形成通路沟槽（4）和支撑沟槽（5）。 支撑沟槽通过牺牲层（12）和下蚀刻停止层更深地延伸并被填充。 牺牲层被暴露并被选择性地蚀刻到蚀刻停止层以形成空腔（30）并且实现通过包括填充的支撑沟槽的垂直支撑结构附接到主体衬底的半导体膜。

公开(公告)号：US07816166B1

公开(公告)日：2010-10-19

申请号：US11716082

申请日：2007-03-09

Applicant: Emmanuel P. Quevy

Inventor： Emmanuel P. Quevy

IPC: H01L21/00

CPC classification number: B81C1/0015 ,  B81B2201/0271 ,  B81C1/00595 ,  B81C2201/0136 ,  B81C2201/014

Abstract: A method to form a MEMS structure is described. In an embodiment, a structure having a first release layer between a substrate and a member is provided. A second release layer is adjacent to a sidewall of the member. At least a portion of each of the first and the second release layers is then removed. In one embodiment, the member is formed by a damascene process. In another embodiment, the member is formed by a subtractive process. In a specific embodiment, the second release layer formed adjacent to a sidewall of the member has sub-lithographic dimensions.

Abstract translation: 描述了形成MEMS结构的方法。 在一个实施例中，提供了在基板和构件之间具有第一释放层的结构。 第二释放层与构件的侧壁相邻。 然后去除第一和第二释放层中的每一个的至少一部分。 在一个实施例中，构件通过镶嵌工艺形成。 在另一个实施例中，构件通过减法处理形成。 在具体实施例中，与构件的侧壁相邻形成的第二释放层具有亚光刻尺寸。

公开(公告)号：US20100203737A1

公开(公告)日：2010-08-12

申请号：US12750877

申请日：2010-03-31

Applicant: Yasuhiro MORIKAWA ,  Toshio HAYASHI ,  Koukou SUU

Inventor： Yasuhiro MORIKAWA ,  Toshio HAYASHI ,  Koukou SUU

IPC: H01L21/302

CPC classification number: H01L21/30655 ,  B81C1/00595 ,  B81C2201/014 ,  H01J37/3255 ,  H01J2237/334

Abstract: An etching method and an etching system are adapted to produce a high etch selectivity for a mask, an excellent anisotropic profile and a large etching depth. An etching system according to the invention comprises a floating electrode arranged vis-à-vis a substrate electrode in a vacuum chamber and held in a floating state in terms of electric potential, a material arranged at the side of the floating electrode facing the substrate electrode to form an anti-etching film and a control unit for intermittently applying high frequency power to the floating electrode. An etching method according to the invention uses a material arranged at the side of the floating electrode opposite to the substrate electrode to form an anti-etching film as target and only rare gas as main gas and is adapted to repeat a step of forming a film on the substrate by sputtering by applying high frequency power to the floating electrode and a step of subsequently etching the substrate by suspending the application of high frequency power to the floating electrode and introducing etching gas into the vacuum chamber in a predetermined sequence.

Abstract translation: 蚀刻方法和蚀刻系统适于产生掩模的高蚀刻选择性，优异的各向异性轮廓和大的蚀刻深度。 根据本发明的蚀刻系统包括相对于真空室中的基板电极布置并且在电位方面保持为浮置状态的浮动电极，布置在浮置电极的面向基板电极的一侧的材料 形成抗蚀刻膜和用于间歇地向浮动电极施加高频电力的控制单元。 根据本发明的蚀刻方法使用布置在与基板电极相对的浮动电极侧的材料来形成作为靶的抗蚀刻膜，并且仅将稀有气体作为主要气体，并且适于重复形成膜的步骤 通过向浮动电极施加高频电力而通过溅射在衬底上，以及通过将高频电力施加到浮动电极并以预定顺序将蚀刻气体引入真空室中而随后蚀刻衬底的步骤。

公开(公告)号：US20100149627A1

公开(公告)日：2010-06-17

申请号：US12711594

申请日：2010-02-24

Applicant: Teruo Sasagawa ,  Clarence Chui ,  Manish Kothari ,  SuryaPrakash Ganti ,  Jeffrey B. Sampsell ,  Chun-Ming Wang

Inventor： Teruo Sasagawa ,  Clarence Chui ,  Manish Kothari ,  SuryaPrakash Ganti ,  Jeffrey B. Sampsell ,  Chun-Ming Wang

IPC: G02B26/00 ,  B05D5/12 ,  C23F1/00

CPC classification number: G02B26/0841 ,  B81B2201/042 ,  B81B2203/0307 ,  B81C1/00595 ,  B81C2201/014 ,  G02B26/001

Abstract: A microelectromechanical systems device having support structures formed of sacrificial material surrounded by a protective material. The microelectromechanical systems device includes a substrate having an electrode formed thereon. Another electrode is separated from the first electrode by a cavity and forms a movable layer, which is supported by support structures formed of a sacrificial material.

Abstract translation: 具有由保护材料包围的牺牲材料形成的支撑结构的微机电系统装置。 微机电系统装置包括其上形成有电极的基板。 另一电极通过空腔与第一电极分离，并形成可移动层，该可移动层由牺牲材料形成的支撑结构支撑。

公开(公告)号：US20090298293A1

公开(公告)日：2009-12-03

申请号：US12496748

申请日：2009-07-02

Applicant: Dirk Marteen Knotter ,  Arnoldus Den Dekker ,  Ronald Koster ,  Robertus T. F. Van Schaijk

Inventor： Dirk Marteen Knotter ,  Arnoldus Den Dekker ,  Ronald Koster ,  Robertus T. F. Van Schaijk

IPC: H01L21/306

CPC classification number: B81C1/00595 ,  B81C2201/014

Abstract: The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.

Abstract translation: 本发明涉及一种用于蚀刻蚀刻层中的特征的方法，该蚀刻层的特征厚度大于2微米，从蚀刻剂的初始接触面到蚀刻层的相对底面，蚀刻层的横向特征位置 并且在底面具有临界横向延伸。 该方法包括在基底层上的横向特征位置处制造掩模层材料的掩模特征，掩模特征具有临界横向延伸。 蚀刻层在相对于掩模层材料可选择性蚀刻的蚀刻层材料上沉积到掩模特征和基底层上大于2微米的厚度。 然后，使用相对于掩模层材料选择性去除蚀刻层材料的蚀刻剂，在第一横向位置处蚀刻该特征，其横向延伸大于临界横向延伸。