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公开(公告)号：US07154339B2
公开(公告)日：2006-12-26
申请号：US10514900
申请日：2003-05-19
IPC分类号： H03F3/68
摘要： An RF power amplifier according to the invention comprises a plurality of parallel output transistors (HBT,1,1 to HBT,1,N) connected to a power supply. A plurality of base resistors (Rb,1,1 to Rb,1,N) for the output transistors (HBT,1,1 to HBT,1,N) and a plurality of input capacitors (Cb,1 to Cb,N), each coupled in parallel to receive an RF signal input and connected via at least one additional passive component to the inputs of each corresponding output transistor (HBT,1,1 to HBT,1,N), are provided An output for an RF output signal is obtained from the parallel connection of the output transistors (HBT,1,1 to HBT,1,N). The transistors (HBT,1,1 to HBT,1,N) are heterojunction bipolar transistors.
摘要翻译： 根据本发明的RF功率放大器包括连接到电源的多个并联输出晶体管（HBT，1,1至HBT，1，N）。 用于输出晶体管（HBT，1,1至HBT，1，N）和多个输入电容器（Cb，1至Cb，N）的多个基本电阻器（Rb，1,1至Rb，1，N） ，每个并联耦合以接收经由至少一个附加无源分量输入并连接到每个对应的输出晶体管（HBT，1,1至HBT，1，N）的输入的RF信号。RF输出的输出 信号从输出晶体管（HBT，1,1至HBT，1，N）的并联连接获得。 晶体管（HBT，1,1至HBT，1，N）是异质结双极晶体管。
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2.发明授权Etching with improved control of critical feature dimensions at the bottom of thick layers 有权蚀刻，改善了厚层底部关键特征尺寸的控制公开(公告)号：US08282845B2
公开(公告)日：2012-10-09
申请号：US12496748
申请日：2009-07-02
IPC分类号： C03C15/00
CPC分类号： B81C1/00595 , B81C2201/014
摘要： The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.
摘要翻译： 本发明涉及一种用于蚀刻蚀刻层中的特征的方法，该蚀刻层的特征厚度大于2微米，从蚀刻剂的初始接触面到蚀刻层的相对底面，蚀刻层的横向特征位置 并且在底面具有临界横向延伸。 该方法包括在基底层上的横向特征位置处制造掩模层材料的掩模特征，掩模特征具有临界横向延伸。 蚀刻层在相对于掩模层材料可选择性蚀刻的蚀刻层材料上沉积到掩模特征和基底层上大于2微米的厚度。 然后，使用相对于掩模层材料选择性去除蚀刻层材料的蚀刻剂，在第一横向位置处蚀刻该特征，其横向延伸大于临界横向延伸。
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3.发明申请Etching with Improved Control of Critical Feature Dimensions at the Bottom of Thick Layers 有权通过改进厚层底部关键特征尺寸的控制进行蚀刻公开(公告)号：US20090298293A1
公开(公告)日：2009-12-03
申请号：US12496748
申请日：2009-07-02
IPC分类号： H01L21/306
CPC分类号： B81C1/00595 , B81C2201/014
摘要： The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.
摘要翻译： 本发明涉及一种用于蚀刻蚀刻层中的特征的方法，该蚀刻层的特征厚度大于2微米，从蚀刻剂的初始接触面到蚀刻层的相对底面，蚀刻层的横向特征位置 并且在底面具有临界横向延伸。 该方法包括在基底层上的横向特征位置处制造掩模层材料的掩模特征，掩模特征具有临界横向延伸。 蚀刻层在相对于掩模层材料可选择性蚀刻的蚀刻层材料上沉积到掩模特征和基底层上大于2微米的厚度。 然后，使用相对于掩模层材料选择性去除蚀刻层材料的蚀刻剂，在第一横向位置处蚀刻该特征，其横向延伸大于临界横向延伸。
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公开(公告)号：US20060186964A1
公开(公告)日：2006-08-24
申请号：US10560638
申请日：2004-06-15
IPC分类号： H03F3/04
CPC分类号： H03F3/21 , H03F1/0261 , H03F1/30 , H03F3/3432 , H03F2200/453 , H03F2200/462
摘要： A detection circuit for detecting the output power of a power amplifier comprises a first current minor transistor (Ti 1) having a base, which is connectable to a power transistor (T10), and a collector, a RF detection means (RF-det) for detecting the RF current flowing through the current mirror transistor (T11). Said RF detection means (RFdet) is connected to the collector of said first current mirror transistor (T11). Said detection circuit further comprises a biasing means (bias-RF-det) for biasing said RF detection means (RF-det), wherein said biasing means is connected to said collector of said first current mirror (T11) and said RF detection means (RF-det).
摘要翻译： 用于检测功率放大器的输出功率的检测电路包括具有可连接到功率晶体管（T10）的基极的第一电流次级晶体管（Ti 1）和集电极，RF检测装置（RF-det ），用于检测流过电流镜晶体管（T11）的RF电流。 所述RF检测装置（RFdet）连接到所述第一电流镜晶体管（T11）的集电极。 所述检测电路还包括用于偏置所述RF检测装置（RF-det）的偏置装置（偏置RF-det），其中所述偏置装置连接到所述第一电流镜（T11）的所述集电极，并且所述RF检测装置 （RF-det）。
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5.发明授权Method of manufacturing a semiconductor device having a semiconductor body with field insulation regions formed by grooves filled with insulating material 失效具有半导体本体的半导体器件的制造方法，该半导体器件具有由绝缘材料填充的沟槽形成的场绝缘区域
公开(公告)号：US5554256A
公开(公告)日：1996-09-10
申请号：US310824
申请日：1994-09-22
IPC分类号： H01L21/31 , H01L21/308 , H01L21/76 , H01L21/00
CPC分类号： H01L21/308 , H01L21/76
摘要： A method of manufacturing a semiconductor device comprising a semiconductor body (1) with field insulation regions (14) formed by grooves (10; 24) filled with an insulating material (13) is disclosed. The grooves (10; 24) are etched into the semiconductor body (1) with the use of an etching mask (9) formed on an auxiliary layer (6) provided on a surface (5) of the semiconductor body (1). The auxiliary layer (6) is removed from the portion (11) of the surface (5) situated next to the etching mask (9) before the grooves (10; 24) are etched into the semiconductor body (1), and the auxiliary layer (6) is removed from the edge (12) of the surface (5) situated below the etching mask (9) after the grooves (10; 24) have been etched into the semiconductor body. Furthermore, a layer (13) of the insulating material is deposited on the semiconductor body (1), whereby the grooves (10; 24) are filled and the edge (12) of the surface (5) situated below the etching mask (9) is covered. Then the semiconductor body is subjected to a treatment whereby material is taken off parallel to the surface (5) down to the auxiliary layer (6), and finally the remaining portion of the auxiliary layer (6) is removed. Field insulation regions are thus formed which extend over an edge (12) of the active regions (15) surrounded by the field insulation regions (14) with a strip (18) which has no overhanging edge.
摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件包括具有由绝缘材料（13）填充的沟槽（10; 24）形成的场绝缘区域（14）的半导体本体（1）。 使用形成在设置在半导体本体（1）的表面（5）上的辅助层（6）上的蚀刻掩模（9），将凹槽（10; 24）蚀刻到半导体本体（1）中。 在凹槽（10; 24）被蚀刻到半导体本体（1）中之前，从邻近蚀刻掩模（9）的表面（5）的部分（11）去除辅助层（6），并且辅助层 在凹槽（10; 24）被蚀刻到半导体本体中之后，从位于蚀刻掩模（9）下方的表面（5）的边缘（12）去除层（6）。 此外，绝缘材料的层（13）沉积在半导体本体（1）上，由此填充凹槽（10; 24），并且位于蚀刻掩模（9）下方的表面（5）的边缘（12） ）被覆盖。 然后对半导体体进行处理，由此将材料平行于表面（5）取下到辅助层（6），最后除去辅助层（6）的剩余部分。 这样形成了场绝缘区域，该区域由具有不突出边缘的条带（18）在由绝缘区域（14）包围的有源区域（15）的边缘（12）上延伸。
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6.发明授权
公开(公告)号：US5508213A
公开(公告)日：1996-04-16
申请号：US326440
申请日：1994-10-20
IPC分类号： H01L29/73 , H01L21/225 , H01L21/285 , H01L21/306 , H01L21/331 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/28525 , Y10S148/009
摘要： A method of manufacturing a semiconductor device whereby on a surface (3) of a semiconductor body (1) a conductor track (21) of polycrystalline silicon insulated from the surface (3) is provided in a layer of doped polycrystalline silicon (11) provided on a layer of insulating material (10), and whereby a strip of polycrystalline silicon (19, 35) is formed between an edge (18) of the conductor (21) and a portion (24, 34) of the surface (3) adjoining the edge (18), after which a semiconductor zone (30) is formed through diffusion of dopant from the conductor (21) through the strip (19, 35) into the semiconductor body (1). During the formation of the insulated conductor (21) and the strip of polycrystalline silicon (19, 35), a window (15) is etched into the layer of polycrystalline silicon (11) by means of a first etching mask (13), after which the insulating layer (10) is removed from the surface (3) within the window (15), the window (15) is provided at its edge (18) with a strip of polycrystalline silicon (19, 35), and the conductor (21) is etched into the layer of polycrystalline silicon (11) by means of a second etching mask (20), this second etching mask (20) covering at least a portion of the edge (18) of the window (15). Further conductors (22, 23) may be formed in the polycrystalline layer (11) next to the insulated conductor (21), all conductors (21, 22, 23) being given dimensions such as defined by the second etching mask (20).
摘要翻译： 一种制造半导体器件的方法，其中在半导体本体（1）的与表面（3）绝缘的多晶硅的导体轨道（21）的表面（3）上设置有提供的掺杂多晶硅层（11） 在一层绝缘材料（10）上，并且由此在导体（21）的边缘（18）和表面（3）的部分（24,34）之间形成多晶硅条（19,35） 邻接边缘（18），之后通过掺杂剂从导体（21）穿过条带（19,35）扩散到半导体本体（1）中而形成半导体区域（30）。 在形成绝缘导体（21）和多晶硅条（19,35）期间，通过第一蚀刻掩模（13）将窗口（15）蚀刻到多晶硅层（11）中，之后 其中绝缘层（10）从窗口（15）内的表面（3）移除，窗口（15）在其边缘（18）处设置有多晶硅条（19,35），并且导体 （21）通过第二蚀刻掩模（20）蚀刻到多晶硅层（11）中，该第二蚀刻掩模（20）覆盖窗口（15）的边缘（18）的至少一部分。 另外的导体（22,23）可以形成在绝缘导体（21）旁边的多晶层（11）中，所有的导体（21,22,23）都具有由第二蚀刻掩模（20）限定的尺寸。
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公开(公告)号：US20080239597A1
公开(公告)日：2008-10-02
申请号：US11575727
申请日：2005-09-14
申请人： Adrianus Van Bezooijen , Ronald Koster , Rob Mathijs Heeres , Dmitry Paviovich Prikhodko , Bart Balm
发明人： Adrianus Van Bezooijen , Ronald Koster , Rob Mathijs Heeres , Dmitry Paviovich Prikhodko , Bart Balm
CPC分类号： H03F1/52 , H03F2200/435 , H03F2200/471
摘要： A peak voltage protection circuit for protecting an associated High Voltage NPN transistor (T3) against breakdown, the protection circuit comprising a Low Voltage NPN element (T15) for sensing a sensor voltage related to a base-collector voltage of the associated High Voltage NPN transistor (T3). The circuit further comprises an activation circuit for limiting the base-collector voltage of the associated High Voltage NPN transistor (T3) upon triggering. The Low Voltage NPN element (15) is coupled to the activation circuit for triggering it upon the sensor voltage exceeding a breakdown voltage of the Low Voltage NPN transistor (T15).
摘要翻译： 一种用于保护相关联的高电压NPN晶体管（T 3）免于击穿的峰值电压保护电路，所述保护电路包括用于感测与相关联的高电压的基极 - 集电极电压相关的传感器电压的低电压NPN元件（T 15） NPN晶体管（T 3）。 电路还包括用于在触发时限制相关联的高电压NPN晶体管（T 3）的基极 - 集电极电压的激活电路。 低电压NPN元件（15）耦合到激活电路，以在传感器电压超过低电压NPN晶体管（T15）的击穿电压时触发它。
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公开(公告)号：US07274206B2
公开(公告)日：2007-09-25
申请号：US10560638
申请日：2004-06-15
申请人： Dmitry Pavlovich Prikhodko , Adrianus Van Bezooijen , Christophe Chanlo , John Joseph Hug , Ronald Koster
发明人： Dmitry Pavlovich Prikhodko , Adrianus Van Bezooijen , Christophe Chanlo , John Joseph Hug , Ronald Koster
IPC分类号： G01R31/26
CPC分类号： H03F3/21 , H03F1/0261 , H03F1/30 , H03F3/3432 , H03F2200/453 , H03F2200/462
摘要： A detection circuit for detecting the output power of a power amplifier comprises a first current minor transistor (Ti 1) having a base, which is connectable to a power transistor (T10), and a collector, a RF detection means (RF-det) for detecting the RF current flowing through the current mirror transistor (T11). Said RF detection means (RFdet) is connected to the collector of said first current mirror transistor (T11). Said detection circuit further comprises a biasing means (bias-RF-det) for biasing said RF detection means (RF-det), wherein said biasing means is connected to said collector of said first current mirror (T11) and said RF detection means (RF-det).
摘要翻译： 用于检测功率放大器的输出功率的检测电路包括具有可连接到功率晶体管（T10）的基极的第一电流次级晶体管（Ti 1）和集电极，RF检测装置（RF-det ），用于检测流过电流镜晶体管（T11）的RF电流。 所述RF检测装置（RFdet）连接到所述第一电流镜晶体管（T11）的集电极。 所述检测电路还包括用于偏置所述RF检测装置（RF-det）的偏置装置（偏置RF-det），其中所述偏置装置连接到所述第一电流镜（T11）的所述集电极，并且所述RF检测装置 （RF-det）。
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公开(公告)号：US5970332A
公开(公告)日：1999-10-19
申请号：US623384
申请日：1996-03-27
IPC分类号： H01L29/43 , H01L21/28 , H01L21/8249 , H01L27/06 , H01L29/78 , H01L21/8238
CPC分类号： H01L21/8249
摘要： A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is destined for the bipolar transistor and a second region (7) for the MOS transistor. The second region is provided with a gate dielectric (10). Then an electrode layer of non-crystalline silicon (11) is provided on the surface, which electrode layer is provided with a doping and in which electrode layer subsequently an emitter electrode (12) is formed on the first region and a gate electrode (13) on the second region. The electrode layer is provided with a doping by means of a treatment whereby a first dopant is provided at the area of the first region and a second dopant at the area of the second region, the first dopant being provided to a concentration such that the emitter zone of the transistor can be formed through diffusion from the emitter electrode to be formed in the electrode layer, while the second dopant is provided to a concentration lower than that of the first dopant. Owing to the comparatively low doping level, gate oxide breakdown is prevented during plasma etching and ion implantation.
摘要翻译： 制造具有双极晶体管（1）的半导体器件的方法和形成在硅体（3）中的MOS晶体管（2），为此目的，提供了一种场致绝缘区域（4） 7）邻接所述主体的表面（5）是相互绝缘的。 第一区域（6）用于双极晶体管和用于MOS晶体管的第二区域（7）。 第二区域设置有栅极电介质（10）。 然后在表面上提供非晶硅（11）的电极层，该电极层设置有掺杂，并且其中电极层随后在第一区域上形成发射电极（12），栅电极（13） ）在第二个地区。 电极层通过处理被提供掺杂，由此在第一区域的区域处提供第一掺杂剂，在第二区域的区域设置第二掺杂剂，第一掺杂剂被提供为使得发射极 晶体管的区域可以通过从要在电极层中形成的发射极电极的扩散而形成，而第二掺杂剂的浓度比第一掺杂剂的浓度低。 由于相对较低的掺杂水平，在等离子体蚀刻和离子注入期间防止栅氧化层击穿。
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10.发明授权公开(公告)号：US08097483B2
公开(公告)日：2012-01-17
申请号：US12682000
申请日：2008-10-15
IPC分类号： H01L21/00
CPC分类号： B81C1/0015 , B81B2203/0307 , B81B2203/0315 , B81C2201/0107 , H01G5/16 , H01G13/00
摘要： Method for manufacturing a capacitor on a substrate, the capacitor including a first electrode (5) and a second electrode (12; 25), the first and second electrodes being separated by a cavity (16; 32), the substrate including an insulating surface layer (3), the first electrode (5) being arranged on the insulating surface layer a first metal body (7a; 20) being adjacent to the first electrode and arranged as anchor of the second electrode (12; 25) the second electrode being arranged as a beam-shaped body (12; 25) located on the first metal body and above the first electrode; the cavity (16; 32) being laterally demarcated by a sidewall of the first metal body.
摘要翻译： 在基板上制造电容器的方法，所述电容器包括第一电极（5）和第二电极（12; 25），所述第一和第二电极由空腔（16; 32）分开，所述基板包括绝缘表面 层（3），所述第一电极（5）在所述绝缘表面层上布置有与所述第一电极相邻并且被布置为所述第二电极（12; 25）的锚定件的第一金属体（7a; 20），所述第二电极为 被布置为位于所述第一金属体上并位于所述第一电极上方的梁状体（12; 25）; 空腔（16; 32）由第一金属体的侧壁横向划分。
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