公开(公告)号：US12213311B2

公开(公告)日：2025-01-28

申请号：US17670685

申请日：2022-02-14

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions, Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally therealong in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines and projections is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines. Other embodiments are disclosed.

公开(公告)号：US12211814B2

公开(公告)日：2025-01-28

申请号：US18212665

申请日：2023-06-21

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Quang Nguyen ,  Christopher Glancey ,  Koustav Sinha ,  Chan H. Yoo

IPC: H01L23/00

Abstract: Semiconductor devices having interconnect structures with conductive elements configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include a plurality of conductive elements made of a first conductive material having a first elastic modulus. The pillar structure can further include a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements. The second conductive material can have a second elastic modulus less than the first elastic modulus.

公开(公告)号：US12211573B2

公开(公告)日：2025-01-28

申请号：US17725025

申请日：2022-04-20

Applicant: Micron Technology, Inc.

Inventor： Kai Wang

IPC: G11C29/12 ,  G11C29/18 ,  G11C29/36 ,  G11C29/46 ,  G11C29/56

Abstract: Systems and methods for filtering data (DQ) signals are described herein. The systems and methods may involve operating a memory to enter a training mode and sending a command to a decoder while the memory is in the training mode. The decoder may generate a command/address waveform in response to the command. The systems and methods may involve transmitting a burst indicator waveform via a first pin of the memory. The burst indicator waveform may be generated by a burst indicator generator of the memory based on the command/address waveform.

公开(公告)号：US12211552B2

公开(公告)日：2025-01-28

申请号：US18121846

申请日：2023-03-15

Applicant: Micron Technology, Inc.

Inventor： Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki ,  Sheyang Ning ,  Jeffrey S. McNeil

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: Described are systems and methods for concurrent slow-fast memory cell programming. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the set of memory cells are electrically coupled to a target wordline and one or more target bitlines; causing a first programming pulse to be performed by applying a first programming voltage to the target wordline; classifying, by a processing device, the set of memory cells into a first subset of memory cells and a second subset of memory cells based on their respective threshold voltages; causing a first bias voltage to be applied to a first target bitline connected to the first subset of memory cells; causing a second bias voltage to be applied to a second target bitline connected to the second subset of memory cells; and causing a second programing voltage to be applied to the target wordline, wherein the second programming voltage exceeds the first programing voltage.

公开(公告)号：US12211545B2

公开(公告)日：2025-01-28

申请号：US17845640

申请日：2022-06-21

Applicant: Micron Technology, Inc.

Inventor： Liang Liu

IPC: G11C11/4093

Abstract: Devices and methods include generating biases for input buffers of a semiconductor device. In some embodiments, the semiconductor device includes an input buffer that buffer datas and biasing generation and distribution circuitry that generates and distributes a bias current to the input buffer based at least in part on a reference voltage. The biasing generation and distribution circuitry includes dynamic voltage bias circuitry that adjusts the bias current and reference voltage tracking circuitry that controls operation of the dynamic voltage bias circuitry based on the reference voltage.

公开(公告)号：US12210769B2

公开(公告)日：2025-01-28

申请号：US18228065

申请日：2023-07-31

Applicant: Micron Technology, Inc.

Inventor： Giovanni Maria Paolucci

IPC: G06F3/06

Abstract: A memory device includes a memory array and control logic to perform operations including identifying a target cell and a set of cells adjacent to the target cell. Each cell of the set of cells is associated with a respective adjacent cell state. The operations further include determining, for each adjacent cell state, a respective interference value, assigning, based on the respective interference value, each adjacent cell state to a respective bin of a set of state information bins, and in response to determining that each bin of the set of state information bins has at least one adjacent cell state assigned to it, and determining a set of read level offsets for reading the target cell. Each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins.

公开(公告)号：US20250031510A1

公开(公告)日：2025-01-23

申请号：US18908037

申请日：2024-10-07

Applicant: Micron Technology, Inc.

Inventor： Vladimir Odnoblyudov ,  Martin F. Schubert

IPC: H01L27/15 ,  H01L23/60 ,  H01L25/16 ,  H01L33/00 ,  H01L33/38 ,  H01L33/40

Abstract: Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment, a solid state transducer device includes a solid state emitter, and an electrostatic discharge device carried by the solid state emitter. In some embodiments, the electrostatic discharge device and the solid state emitter share a common first contact and a common second contact. In further embodiments, the solid state lighting device and the electrostatic discharge device share a common epitaxial substrate. In still further embodiments, the electrostatic discharge device is positioned between the solid state lighting device and a support substrate.

公开(公告)号：US20250031383A1

公开(公告)日：2025-01-23

申请号：US18788475

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Anna Maria Conti

IPC: H10B63/00 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H10B53/20 ,  H10N70/00 ,  H10N70/20

Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.

公开(公告)号：US20250029924A1

公开(公告)日：2025-01-23

申请号：US18772808

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Roger W. Lindsay

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor device, such as comprising NAND memory structures, can include a substrate with an arrangement of conductive interconnects. A corrugated support can be provided on the substrate, wherein the support comprises a planar first major surface and an opposed second major surface proximal to the substrate, the first major surface including a plurality of vias extending along a first direction, wherein the vias have an inlet at a first major surface of the support and an outlet at the second major surface of the support. An arrangement of flutes can be provided on the second major surface of the support. The flutes can extend along a second direction normal to the first direction. The flutes are separated by voids, and the vias terminate in the voids.

公开(公告)号：US20250029641A1

公开(公告)日：2025-01-23

申请号：US18910412

申请日：2024-10-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. MCNeil ,  Jung-Sheng Hoei

IPC: G11C7/10 ,  G11C7/14 ,  G11C7/22

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.