公开(公告)号：US20180341545A1

公开(公告)日：2018-11-29

申请号：US16053815

申请日：2018-08-03

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Sheng-I Hsu

IPC: G06F11/10 ,  G06F12/02 ,  H03M13/29 ,  H03M13/09 ,  H03M13/13

Abstract: A data storage system includes a processing circuit, a lookup table (LUT), and a decoding circuit. The processing circuit is arranged to receive a first logical block address (LBA) from a host. The LUT is arranged to store a storage address mapping to the first LBA. The decoding circuit is arranged to utilize the storage address to read storage data from a storing circuit, and decode a first data sector in the storage data according to an error checking and correcting code in the storage data, and the first data sector at least comprises a second LBA.

公开(公告)号：US10133664B2

公开(公告)日：2018-11-20

申请号：US15497217

申请日：2017-04-26

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: G06F12/02 ,  G06F3/06 ,  G06F11/10 ,  G11C7/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C16/08

Abstract: A method for accessing a flash memory module is provide. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of the flash memory chips; and allocating a buffer memory space to store a plurality of temporary parities generated when data is written into the at least one first super block.

公开(公告)号：US20180314428A1

公开(公告)日：2018-11-01

申请号：US16028891

申请日：2018-07-06

Applicant: SILICON MOTION, INC.

Inventor： Sheng-Yuan Huang ,  Yu-Ping Chang

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0679 ,  G11C29/44 ,  G11C29/52 ,  G11C29/76 ,  G11C29/804 ,  G11C2029/4402

Abstract: A method for screening bad data columns in a data storage medium comprising a plurality of data columns includes: labeling or recording a plurality of bad data columns as a bad data column group, wherein the bad data columns are selected from the data columns in the data storage medium, each of the bad data column groups labels or records a position and a number of the bad data columns; determining whether the total number of the bad data columns is greater than a total number of the bad data column groups; and if yes, labeling or recording any two bad data columns of the bad data columns spaced apart by P data columns as one of the bad data column groups, wherein P is a positive integer.

公开(公告)号：US20180300061A1

公开(公告)日：2018-10-18

申请号：US15868535

申请日：2018-01-11

Applicant: Silicon Motion, Inc.

Inventor： Tzu-Wei HSU

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F3/0608 ,  G06F3/065 ,  G06F3/0679 ,  G06F13/1657 ,  G06F13/1678 ,  G06F13/28

Abstract: A memory controller includes a central processing unit, an interface logic circuit and an arbiter circuit. The central processing unit includes an internal memory device. The interface logic circuit is coupled to an external memory device and a standard bus. The arbiter circuit is directly coupled to the central processing unit via an SRAM bus. When the central processing unit has to read predetermined data stored in the external memory device, the central processing unit issues a first request to the interface logic circuit. In response to the first request, the interface logic circuit reads the predetermined data from the external memory device and transmits the predetermined data to the arbiter circuit via the standard bus. The arbiter circuit transfers the predetermined data directly to the central processing unit via the SRAM bus to write the predetermined data in the internal memory device.

公开(公告)号：US10102904B2

公开(公告)日：2018-10-16

申请号：US15679178

申请日：2017-08-17

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hsiao-Te Chang ,  Wen-Long Wang

IPC: G11C11/56 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26

Abstract: A memory access module for performing memory access management of a storage device includes a plurality of storage cells. Each storage cell has a number of possible bit(s) directly corresponding to possible states of the storage cell. The memory access module further includes: a read only memory for storing a program code; and a microprocessor, coupled to the read only memory, for executing the program code to perform the following steps: performing a plurality of sensing operations, wherein a first sensing operation corresponds to a first sensing voltage, and each subsequent sensing operation corresponds to a sensing voltage determined according to a result of the previous sensing operation; using the plurality of sensing operations to generate a first digital value and a second digital value of a storage cell; using the first and the second digital value to obtain soft information of a same bit stored in the storage cell; and using the soft information to perform soft decoding.

公开(公告)号：US20180275915A1

公开(公告)日：2018-09-27

申请号：US15863898

申请日：2018-01-06

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7205

Abstract: The invention introduces a method for regular and garbage-collection data access, performed by a processing unit, including at least the following steps: configuring a data buffer as a first type when performing a data access operation of a regular data access mode; and configuring the data buffer as a second type when performing a data access operation of a garbage-collection data access mode.

公开(公告)号：US20180275914A1

公开(公告)日：2018-09-27

申请号：US15863894

申请日：2018-01-06

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/7205

Abstract: The invention introduces a method for garbage collection, performed by a processing unit, including at least the following steps: executing instructions of a GC (garbage collection) process to direct a first access interface to read data from a storage unit, collect good data from the read data and direct the first access interface to program the good data into a spare block of the storage unit. During the GC process, each time that a timer has counted to a time period, the processing unit directs a second access interface to clock a portion of data requested by a host device out to the host device and resets the timer.

公开(公告)号：US20180260151A1

公开(公告)日：2018-09-13

申请号：US15848973

申请日：2017-12-20

Applicant: Silicon Motion, Inc.

Inventor： Sheng-I Hsu

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0638 ,  G06F3/0673 ,  G06F21/6218

Abstract: A security mechanism for a data storage device. The data storage device includes a nonvolatile memory and a control unit. The control unit uses a dynamic random access memory at a host side with an encryption mechanism when operating the nonvolatile memory. The control unit protects keys of the encryption mechanism within the data storage device to isolate the keys from the host.

公开(公告)号：US20180260137A1

公开(公告)日：2018-09-13

申请号：US15863889

申请日：2018-01-06

Applicant: Silicon Motion, Inc.

Inventor： Tai-Yu TSOU ,  Po-Chia CHU

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7211

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller receives a read command arranged to read data from a host, determines a plurality of read tasks by analyzing the read command, and determines task time of each of the read tasks according to the number of the read tasks and an I/O latency time. In a first read task of the read tasks, the controller reads a part of the data and transmits the read part to the host, and executes a first maintenance process according to a predetermined condition, wherein the predetermined condition includes a remain time and the remain time is the task time minus the time spent by the first read task.

公开(公告)号：US20180259580A1

公开(公告)日：2018-09-13

申请号：US15813553

申请日：2017-11-15

Applicant: Silicon Motion, Inc.

Inventor： Hung-Sen KUO ,  Te-Wei CHEN ,  Hung-Sheng CHANG ,  Ming-Wan KUAN

IPC: G01R31/319 ,  G01R31/28 ,  G01R31/3177 ,  G01R31/3183

CPC classification number: G01R31/31924 ,  G01R31/2879 ,  G01R31/3008 ,  G01R31/3177 ,  G01R31/318314

Abstract: A circuit test method for a test device to test a device under test is provided. The circuit test method includes the steps of applying zero volts to a plurality of power pins of the device under test; applying a test voltage to a first signal pin among a plurality of signal pins of the device under test; and measuring a current on a second signal pin among the plurality of signal pins of the device under test and determining whether there is a leakage current in the device under test.