公开(公告)号：US20220332571A1

公开(公告)日：2022-10-20

申请号：US17709932

申请日：2022-03-31

Applicant: XINTEC INC.

Inventor： Yu-Tang SHEN ,  Shun-Wen LONG ,  Chih-Hung CHO ,  Hsing-Yuan CHU

IPC: B81C99/00 ,  B32B43/00

Abstract: An operation method of a semiconductor removing apparatus includes moving a semiconductor structure to a stage, wherein the semiconductor structure includes a lower substrate, a cap, and a micro electro mechanical system (MEMS) structure between the lower substrate and the cap, and the cap has a diced portion; pulling, by a clamp assembly, a tape of a tape roll from a first side of the stage to a second side of the stage opposite to the first side, such that the tape is attached to the cap of the semiconductor structure; and pulling, by the clamp assembly, the tape of the tape roll from the second side of the stage back to the first side of the stage, such that the diced portion of the cap separates from the semiconductor structure.

公开(公告)号：US11387201B2

公开(公告)日：2022-07-12

申请号：US17023199

申请日：2020-09-16

Applicant: XINTEC INC.

Inventor： Po-Han Lee ,  Chia-Ming Cheng ,  Jiun-Yen Lai ,  Ming-Chung Chung ,  Wei-Luen Suen

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L21/3213

Abstract: A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.

公开(公告)号：US11137559B2

公开(公告)日：2021-10-05

申请号：US16851099

申请日：2020-04-17

Applicant: XINTEC INC.

Inventor： Jiun-Yen Lai ,  Yu-Ting Huang ,  Hsing-Lung Shen ,  Tsang-Yu Liu ,  Hui-Hsien Wu

IPC: G02B6/42

Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.

公开(公告)号：US11107759B2

公开(公告)日：2021-08-31

申请号：US17037151

申请日：2020-09-29

Applicant: XINTEC INC.

Inventor： Wei-Luen Suen ,  Jiun-Yen Lai ,  Hsing-Lung Shen ,  Tsang-Yu Liu

IPC: H01L23/498 ,  H01L21/48

Abstract: A chip package includes a lower substrate, a first silicon nitride substrate, a bonding layer, an upper substrate, a first functional layer, a transparent conductive layer, an isolation layer, and a first conductive pad. The supporting layer is located between the lower substrate and the first silicon nitride substrate, and is made of a material including Benzocyclobutene (BCB). The upper substrate is located on the first silicon nitride substrate. The first functional layer is located between the upper substrate and the first silicon nitride substrate. The transparent conductive layer is located on the upper substrate. The isolation layer covers the upper substrate and the transparent conductive layer. The first conductive pad is located in the isolation layer and in electrical contact with the transparent conductive layer.

公开(公告)号：US20210210538A1

公开(公告)日：2021-07-08

申请号：US17133636

申请日：2020-12-24

Applicant: XINTEC INC.

Inventor： Jiun-Yen LAI ,  Wei-Luen SUEN ,  Hsing-Lung SHEN ,  Yu-Ting HUANG

IPC: H01L27/146

Abstract: A chip package is provided. The chip package includes a first substrate and a second substrate disposed over the first substrate. The first substrate and the second substrate have a lower surface and an upper surface, and the second substrate includes a first recess region surrounding the second substrate. The first recess region has a tapered sidewall and a bottom surface that is between the lower and upper surfaces of the second substrate. The chip package also includes at least one conductive pad disposed on the upper surface of the second substrate and a redistribution layer (RDL) correspondingly disposed on the conductive pad. The RDL is extended from the conductive pad onto the bottom surface of the first recess region along the tapered sidewall of the first recess region. A method of forming a chip package is also provided.

公开(公告)号：US20210104455A1

公开(公告)日：2021-04-08

申请号：US17037151

申请日：2020-09-29

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Jiun-Yen LAI ,  Hsing-Lung SHEN ,  Tsang-Yu LIU

IPC: H01L23/498 ,  H01L21/48

Abstract: A chip package includes a lower substrate, a first silicon nitride substrate, a bonding layer, an upper substrate, a first functional layer, a transparent conductive layer, an isolation layer, and a first conductive pad. The supporting layer is located between the lower substrate and the first silicon nitride substrate, and is made of a material including Benzocyclobutene (BCB). The upper substrate is located on the first silicon nitride substrate. The first functional layer is located between the upper substrate and the first silicon nitride substrate. The transparent conductive layer is located on the upper substrate. The isolation layer covers the upper substrate and the transparent conductive layer. The first conductive pad is located in the isolation layer and in electrical contact with the transparent conductive layer.

公开(公告)号：US10461117B2

公开(公告)日：2019-10-29

申请号：US15848600

申请日：2017-12-20

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chaung-Lin Lai

IPC: H01L27/146 ,  H01L21/683 ,  H01L23/00

Abstract: A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.

公开(公告)号：US10446504B2

公开(公告)日：2019-10-15

申请号：US15980577

申请日：2018-05-15

Applicant: XINTEC INC.

Inventor： Chia-Ming Cheng ,  Po-Han Lee ,  Wei-Chung Yang ,  Kuan-Jung Wu ,  Shu-Ming Chang

IPC: H01L23/52 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L23/04 ,  H01L27/146

Abstract: A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.

公开(公告)号：US10424540B2

公开(公告)日：2019-09-24

申请号：US15724058

申请日：2017-10-03

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Po-Han Lee ,  Chia-Ming Cheng ,  Hsin-Yen Lin

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/495 ,  H01L27/146

Abstract: A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.

公开(公告)号：US20190273175A1

公开(公告)日：2019-09-05

申请号：US16291637

申请日：2019-03-04

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Po-Han LEE ,  Chien-Min LIN ,  Yi-Rong HO

IPC: H01L31/12 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/18

Abstract: A chip package includes a chip, a sidewall structure that has a first light-shielding layer, a second light-shielding layer, and a cover. The chip has a light emitter and a light receiver that are located on a top surface of the chip. The sidewall structure is located on the top surface of the chip and has two aperture areas. The light emitter and the light receiver are respectively located in the two aperture areas. The sidewall structure surrounds the light emitter and the light receiver, and at least one surface of the sidewall structure has the first light-shielding layer. The second light-shielding layer is located between the chip and the sidewall structure. The cover is located on a surface of the sidewall structure facing away from the chip, and at least covers the light receiver and the sidewall structure that surrounds the light receiver.