公开(公告)号：US09570398B2

公开(公告)日：2017-02-14

申请号：US13895219

申请日：2013-05-15

Applicant: XINTEC INC.

Inventor： Shu-Ming Chang ,  Yu-Ting Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/538 ,  H01L21/78 ,  H01L23/48 ,  B81B7/00 ,  H01L23/00 ,  H01L21/683 ,  H01L23/60

CPC classification number: H01L23/5384 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/481 ,  H01L23/60 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05617 ,  H01L2224/05624 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/10155 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2224/80 ,  H01L2224/83 ,  H01L21/304 ,  H01L21/76898 ,  H01L2221/68304 ,  H01L2224/0231 ,  H01L2224/11

Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一基板; 设置在其上的第二基板，其中所述第二基板包括下半导体层，上半导体层和绝缘层，并且所述下半导体层的一部分与所述第一基板上的至少一个焊盘电接触; 导电层，其设置在所述第二基板的所述上半导体层上并电连接到所述下半导体层与所述至少一个焊盘电接触的部分; 从上半导体层向下半导体层延伸并延伸到下半导体层的开口; 以及设置在所述上​​半导体层和所述导电层上的保护层，其中所述保护层延伸到所述开口的侧壁的一部分上，并且不覆盖所述开口中的下半导体层。

公开(公告)号：US09334156B2

公开(公告)日：2016-05-10

申请号：US14747507

申请日：2015-06-23

Applicant: XINTEC INC.

Inventor： Chien-Min Lin ,  Yu-Ting Huang ,  Chen-Ning Fu ,  Yen-Shih Ho

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81C1/00182 ,  B81C1/00269 ,  B81C2201/0197 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package includes a semiconductor chip, an interposer, a polymer adhesive supporting layer, a redistribution layer and a packaging layer. The semiconductor chip has a sensor device and a conductive pad electrically connected to the sensing device, and the interposer is disposed on the semiconductor chip. The interposer has a trench and a through hole, which the trench exposes a portion of the sensing device, and the through hole exposes the conductive pad. The polymer adhesive supporting layer is interposed between the semiconductor chip and the interposer, and the redistribution layer is disposed on the interposer and in the through hole to be electrically connected to the conductive pad. The packaging layer covers the interposer and the redistribution layer, which the packaging layer has an opening exposing the trench.

Abstract translation: 芯片封装包括半导体芯片，插入件，聚合物粘合剂支撑层，再分布层和包装层。 半导体芯片具有传感器装置和与感测装置电连接的导电焊盘，并且插入器设置在半导体芯片上。 插入器具有沟槽和通孔，沟槽暴露感测装置的一部分，并且通孔暴露导电垫。 聚合物粘合剂支撑层插入在半导体芯片和插入件之间，并且再分配层设置在插入件上和通孔中以与导电焊盘电连接。 包装层覆盖插入件和再分配层，其中封装层具有露出沟槽的开口。

公开(公告)号：US09972584B2

公开(公告)日：2018-05-15

申请号：US15140199

申请日：2016-04-27

Applicant: XINTEC INC.

Inventor： Hsing-Lung Shen ,  Jiun-Yen Lai ,  Yu-Ting Huang

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/768 ,  H01L23/31 ,  H01L31/0203 ,  H01L21/78 ,  H01L31/0216 ,  H01L33/62 ,  H01L23/48 ,  H01L21/56

CPC classification number: H01L23/564 ,  H01L21/561 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/32 ,  H01L22/34 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/481 ,  H01L31/0203 ,  H01L31/02164 ,  H01L33/62 ,  H01L2224/11

Abstract: A chip package includes a chip, a dam layer, a carrier substrate and a light shielding passivation layer. The chip has a first surface and a second surface opposite to the first surface, and a side surface is disposed between the first surface and the second surface. The dam layer is disposed on the first surface, and the carrier substrate is disposed on the dam layer. The light shielding passivation layer is disposed under the second surface and extended into the carrier substrate to cover the side surface of the chip.

公开(公告)号：US09337097B2

公开(公告)日：2016-05-10

申请号：US14225336

申请日：2014-03-25

Applicant: XINTEC INC.

Inventor： Yu-Ting Huang

IPC: H01L21/78 ,  H01L23/31 ,  H01L23/482 ,  H01L23/552 ,  H01L27/146 ,  H01L21/56 ,  H01L23/60 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/482 ,  H01L23/552 ,  H01L23/60 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14627 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/0001 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A chip package includes: a substrate; a signal pad and a ground pad disposed on the substrate; a first and a second conducting layers disposed on the substrate and electrically connected to the signal pad and the ground pad, respectively, wherein the first and the second conducting layers extend from an upper surface of the substrate towards a lower surface of the substrate along a first and a second side surfaces of the substrate, respectively, and the first and the second conducting layers protrude from the lower surface; and a protection layer disposed on the substrate, wherein the protection layer completely covers the entire portion of the first conducting layer located on the first side surface of the substrate, and the entire portion of the second conducting layer located on the second side surface of the substrate is not covered by the protection layer.

Abstract translation: 芯片封装包括：基板; 信号焊盘和设置在所述基板上的接地焊盘; 第一导电层和第二导电层，其分别设置在所述基板上并电连接到所述信号焊盘和所述接地焊盘，其中所述第一和第二导电层沿着所述第一和第二导电层从所述基板的上表面延伸到所述基板的下表面 第一和第二侧面分别与第一和第二导电层从下表面突出; 以及设置在所述基板上的保护层，其中所述保护层完全覆盖位于所述基板的所述第一侧表面上的所述第一导电层的整个部分，并且所述第二导电层的位于所述基板的第二侧表面上的整个部分 衬底不被保护层覆盖。

公开(公告)号：US08785247B2

公开(公告)日：2014-07-22

申请号：US13893015

申请日：2013-05-13

Applicant: Xintec Inc.

Inventor： Yu-Lung Huang ,  Yu-Ting Huang

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L31/0203 ,  B81B7/0077 ,  H01L23/10 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2924/01005 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00

Abstract: According to an embodiment, a chip package is provided, which includes: a substrate having a first surface and a second surface; a device region formed in the substrate; a passivation layer formed overlying the first surface of the substrate; at least a polymer planarization layer formed overlying the passivation layer; a package substrate disposed overlying the first surface of the substrate; and a spacer layer disposed between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a cavity overlying the substrate, wherein the polymer planar layer does not extends to an outer edge of the spacer layer.

Abstract translation: 根据实施例，提供一种芯片封装，其包括：具有第一表面和第二表面的基板; 形成在所述基板中的器件区域; 形成在衬底的第一表面上的钝化层; 至少形成在所述钝化层上的聚合物平坦化层; 封装基板，设置在所述基板的第一表面上方; 以及间隔层，其设置在所述封装衬底和所述钝化层之间，其中所述间隔层和所述封装衬底围绕覆盖所述衬底的空腔，其中所述聚合物平面层不延伸到所述间隔层的外边缘。

公开(公告)号：US11137559B2

公开(公告)日：2021-10-05

申请号：US16851099

申请日：2020-04-17

Applicant: XINTEC INC.

Inventor： Jiun-Yen Lai ,  Yu-Ting Huang ,  Hsing-Lung Shen ,  Tsang-Yu Liu ,  Hui-Hsien Wu

IPC: G02B6/42

Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.

公开(公告)号：US09334158B2

公开(公告)日：2016-05-10

申请号：US13900081

申请日：2013-05-22

Applicant: XINTEC INC.

Inventor： Yu-Ting Huang ,  Shu-Ming Chang ,  Yen-Shih Ho ,  Tsang-Yu Liu

IPC: H01L23/48 ,  B81B7/00 ,  H01L21/64 ,  H01L23/498 ,  H01L23/525 ,  H01L23/00

CPC classification number: B81B7/0077 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/64 ,  H01L23/481 ,  H01L23/498 ,  H01L23/525 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06182 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

Abstract translation: 本发明的实施例提供一种芯片封装，包括：第一半导体衬底; 设置在所述第一半导体衬底上的第二半导体衬底，其中所述第二半导体衬底包括下半导体层，上半导体层和位于所述下半导体层和所述上半导体层之间的绝缘层，以及所述下半导体 层与第一半导体衬底上的至少焊盘电接触; 信号导通结构，设置在所述第一半导体衬底的下表面上，其中所述信号导电结构电连接到所述第一半导体衬底上的信号焊盘; 以及导电层，其设置在所述第二半导体衬底的所述上半导体层上并与所述下半导体层的与所述第一半导体衬底上的所述至少一个焊盘电接触的部分电接触。

公开(公告)号：US09177905B2

公开(公告)日：2015-11-03

申请号：US14036954

申请日：2013-09-25

Applicant: XINTEC INC.

Inventor： Yu-Ting Huang ,  Tsang-Yu Liu

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/48 ,  B81B7/00 ,  H01L23/31

CPC classification number: H01L23/49827 ,  B81B7/0061 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/481 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A chip package for a sensing element. The chip package includes a substrate having a first surface and a second surface, and a sensing layer having a sensing region disposed on the first surface of the substrate. A conducting pad structure is disposed on the substrate and electrically connected to the sensing region, and a spacer layer is disposed on the first surface of the substrate. A semiconductor substrate is place on the spacer layer. The semiconductor substrate, the spacer layer, and the substrate together surround a cavity on the sensing region. A through-hole extends from a surface of the semiconductor substrate toward the substrate, and connects to the cavity.

Abstract translation: 用于传感元件的芯片封装。 芯片封装包括具有第一表面和第二表面的基板，以及具有设置在基板的第一表面上的感测区域的感测层。 导电焊盘结构设置在基板上并电连接到感测区域，并且间隔层设置在基板的第一表面上。 半导体衬底位于间隔层上。 半导体衬底，间隔层和衬底一起围绕感测区域上的空腔。 通孔从半导体衬底的表面朝向衬底延伸，并连接到空腔。